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authorRonald G. Minnich <rminnich@gmail.com>2004-08-26 16:13:40 +0000
committerRonald G. Minnich <rminnich@gmail.com>2004-08-26 16:13:40 +0000
commit6707a45eb14bf28abd2a38e1b95d30d27262f347 (patch)
treef6add8095bc5deec447bb667efe170320e69d5fc /src/northbridge
parent1ddc8eaddb54b05a9ecb5ffbf9ba3e3264f63ec3 (diff)
downloadcoreboot-6707a45eb14bf28abd2a38e1b95d30d27262f347.tar.xz
just a few changes before we hit the big fun.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i855pm/raminit.c8
-rw-r--r--src/northbridge/intel/i855pm/raminit.h1
-rw-r--r--src/northbridge/intel/i855pm/reset_test.c1
3 files changed, 10 insertions, 0 deletions
diff --git a/src/northbridge/intel/i855pm/raminit.c b/src/northbridge/intel/i855pm/raminit.c
index 4f7ab231fd..5bb3b7f653 100644
--- a/src/northbridge/intel/i855pm/raminit.c
+++ b/src/northbridge/intel/i855pm/raminit.c
@@ -1980,7 +1980,15 @@ static void mem_err {
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
int i;
+ uint32_t mchtst;
/* 1 & 2 Power up and start clocks */
+ /* arg! the parts are memory mapped! For now, just grab address 0xc0000000 as the base, since I want to use
+ * constants, not variables, for this.
+ */
+ mchtst = pci_read_config32(ctrl->d0, 0xf4);
+ mchtst |= (1 << 22);
+ pci_write_config32(ctrl->d0, 0xf4, mchtst);
+
#if DEBUG_RAM_CONFIG
print_debug(ram_enable_1);
print_debug(ram_enable_2);
diff --git a/src/northbridge/intel/i855pm/raminit.h b/src/northbridge/intel/i855pm/raminit.h
index 6e40683066..3bdec56cb5 100644
--- a/src/northbridge/intel/i855pm/raminit.h
+++ b/src/northbridge/intel/i855pm/raminit.h
@@ -1,6 +1,7 @@
#ifndef RAMINIT_H
#define RAMINIT_H
+/* I think the 855 is only four sockets -- RGM */
#define DIMM_SOCKETS 4
struct mem_controller {
device_t d0;
diff --git a/src/northbridge/intel/i855pm/reset_test.c b/src/northbridge/intel/i855pm/reset_test.c
index 29f2d45e8f..7c933c58e3 100644
--- a/src/northbridge/intel/i855pm/reset_test.c
+++ b/src/northbridge/intel/i855pm/reset_test.c
@@ -1,4 +1,5 @@
/* Convert to C by yhlu */
+/* converted to 855 by RGM */
#define MCH_DRC 0x70
#define DRC_DONE (1 << 29)
/* If I have already booted once skip a bunch of initialization */