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| author | Myles Watson <mylesgw@gmail.com> | 2009-02-27 17:51:16 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-02-27 17:51:16 +0000 |
| commit | 678d6140a5f75bde7b5a6b7ef296ebb7a3dda166 (patch) | |
| tree | 6070fe742cda4fd4184ae1d26ecca852a974580c /src/northbridge | |
| parent | a85c0059f3fa5bdce6002f09e99fd70037552119 (diff) | |
| download | coreboot-678d6140a5f75bde7b5a6b7ef296ebb7a3dda166.tar.xz | |
This patch makes several CMOS/NVRAM reads dependent on whether there's a table to read. Otherwise you never know what you'll get from the factory BIOS. There are probably more, but these are the ones compiled into the s2895.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdk8/coherent_ht.c | 3 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit.c | 9 |
2 files changed, 7 insertions, 5 deletions
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index a224f5d7a6..d24a83c68f 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -1597,7 +1597,8 @@ static void coherent_ht_finalize(unsigned nodes) #if CONFIG_LOGICAL_CPUS==1 unsigned total_cpus; - if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */ + if ((!HAVE_OPTION_TABLE) || + read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */ total_cpus = verify_dualcore(nodes); } else { diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 4b4b0e9c82..ea706b8e05 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -598,11 +598,11 @@ static void hw_enable_ecc(const struct mem_controller *ctrl) if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; } - if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { + if (HAVE_OPTION_TABLE && + read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { dcl &= ~DCL_DimmEccEn; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); - } static int is_dual_channel(const struct mem_controller *ctrl) @@ -1146,7 +1146,8 @@ static void order_dimms(const struct mem_controller *ctrl) { unsigned long tom_k, base_k; - if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { + if ((!HAVE_OPTION_TABLE) || + read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { tom_k = interleave_chip_selects(ctrl); } else { print_debug("Interleaving disabled\r\n"); @@ -1450,7 +1451,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; bios_cycle_time = min_cycle_times[ read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { + if (HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; } min_latency = 2; |