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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-05 21:14:23 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-11-11 06:39:13 +0100 |
| commit | 74e03a4fdd597a027e41f826a8f1d9ec5b21c17f (patch) | |
| tree | 3b1fbcc4270b349b3ad1366e7955d533384264f2 /src/northbridge | |
| parent | cfb93e70bf9a97bd7172b82b979d71295f312e88 (diff) | |
| download | coreboot-74e03a4fdd597a027e41f826a8f1d9ec5b21c17f.tar.xz | |
mainboard/asus/kgpe-d16: Enable CC6
Change-Id: Iae1cbe7d3a6471561abfdb8e182bc764c38bb222
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11978
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index c4410443e0..8ed7e3ce87 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -621,7 +621,11 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_config32_dct(PCI_DEV(0, 0x18 + node, 1), node, channel, 0x124, data->f1x124); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x10c, data->f2x10c); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x114, data->f2x114); - write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118); + if (is_fam15h()) + /* Do not set LockDramCfg or CC6SaveEn at this time */ + write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118 & ~(0x3 << 18)); + else + write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x11c, data->f2x11c); write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x1b0, data->f2x1b0); write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, channel, 0x44, data->f3x44); @@ -1013,6 +1017,10 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste /* ECC scrub rate control */ pci_write_config32(PCI_DEV(0, 0x18 + node, 3), 0x58, data->f3x58); + + if (is_fam15h()) + /* Set LockDramCfg and CC6SaveEn */ + write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x118, data->f2x118); } } } |