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| author | Zheng Bao <zheng.bao@amd.com> | 2010-08-31 06:10:54 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2010-08-31 06:10:54 +0000 |
| commit | 9fae99fc4efa0e88f9e601848735ae20a251a862 (patch) | |
| tree | 05ac77f63459096fd2f7edbd061cb2d1e038192d /src/northbridge | |
| parent | bd61a819496200c135d02ed999b229fdd11f6832 (diff) | |
| download | coreboot-9fae99fc4efa0e88f9e601848735ae20a251a862.tar.xz | |
Get Byte65/66 for register manufacture ID code. RegMan1Present will
be used in write levelization training.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 61539da295..0e187621b4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2124,7 +2124,15 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->MirrPresU_NumRegR |= 1 << i; } /* Get byte62: Reference Raw Card information. We dont need it now. */ - /* byte = mctRead_SPD(smbaddr, 62); */ + /* byte = mctRead_SPD(smbaddr, SPD_RefRawCard); */ + /* Get Byte65/66 for register manufacture ID code */ + if ((0x97 == mctRead_SPD(smbaddr, SPD_RegManufactureID_H)) && + (0x80 == mctRead_SPD(smbaddr, SPD_RegManufactureID_L))) { + if (0x16 == mctRead_SPD(smbaddr, SPD_RegManRevID)) + pDCTstat->RegMan2Present |= 1 << i; + else + pDCTstat->RegMan1Present |= 1 << i; + } /* Get Control word values for RC3. We dont need it. */ byte = mctRead_SPD(smbaddr, 70); pDCTstat->CtrlWrd3 |= (byte >> 4) << (i << 2); /* C3 = SPD byte 70 [7:4] */ |