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| author | David W. Hendricks <dwh@lanl.gov> | 2004-03-19 20:05:42 +0000 |
|---|---|---|
| committer | David W. Hendricks <dwh@lanl.gov> | 2004-03-19 20:05:42 +0000 |
| commit | a0be1fc307d65d819d69b7fee2da9b2daa5b444e (patch) | |
| tree | 0d5bb76cd672fb1a114923f45875df876073fecc /src/northbridge | |
| parent | 3bd1f94c769005d21c215a6254ce56fc22dc6ebf (diff) | |
| download | coreboot-a0be1fc307d65d819d69b7fee2da9b2daa5b444e.tar.xz | |
Includes fix from Craig C Forney
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index d7cee69482..e5bcb2d02f 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -924,7 +924,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz sz.side2 = 0; } map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); - map &= ~(0xf << (index + 4)); + map &= ~(0xf << (index * 4)); /* For each base register. * Place the dimm size in 32 MB quantities in the bits 31 - 21. |