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| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-03-14 20:01:51 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-03-14 20:01:51 +0000 |
| commit | a41ff52ba9eceb0ef72eddc8f2c14be5751d85a3 (patch) | |
| tree | 82823eb572ec1c2a2bae80db5451fa57ac9b6e37 /src/northbridge | |
| parent | c994c973c654817f5e764615776b78b84cd21910 (diff) | |
| download | coreboot-a41ff52ba9eceb0ef72eddc8f2c14be5751d85a3.tar.xz | |
Make the pll stuff parameterized.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/gx2/pll_reset.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index 0e3a3caf95..248f422cc0 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -133,15 +133,15 @@ static void pll_reset(void) if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) { print_debug("disable PLL bypass\n\r"); - msr.hi = 0x00001490; - msr.lo = 0x02000030; + msr.hi = PLLMSRhi; + msr.lo = PLLMSRlo; wrmsr(GLCP_SYS_RSTPLL, msr); - msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24)); + msr.lo |= PLLMSRhi2; wrmsr(GLCP_SYS_RSTPLL, msr); print_debug("Reset PLL\n\r"); - msr.lo |= ((1<<14) |(1<<13) | (1<<0)); + msr.lo |= PLLMSRlo2; wrmsr(GLCP_SYS_RSTPLL,msr); print_debug("should not be here\n\r"); } |