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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-11-24 09:31:10 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-11-25 20:02:16 +0000 |
| commit | a9068aa4e058a72b0cdeaffa423db17d7dd09fc6 (patch) | |
| tree | 29c633b7c42b831f0065d6dc3b2a58656cf8c069 /src/northbridge | |
| parent | 48fa9225ca18e6320e032b8eedf81087de224cc4 (diff) | |
| download | coreboot-a9068aa4e058a72b0cdeaffa423db17d7dd09fc6.tar.xz | |
nb/intel/i945/early_init.c: Correct the PEG_LC address of DEV(0:01.0)
This bug/typo was spoted by Felix Held.
As documented in the datasheet, to enable PMEGPE, HPGPE, GENGPE, we need
to write 0x7 into DEV(0:01.0) register "PCI Express-G Legacy Control"
located at 0xec.
Used address at 0x114 to enable GPEs is likely a typo.
Patch not tested.
Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/27307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d516db76b9..39d660bf98 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -701,7 +701,7 @@ static void i945_setup_pci_express_x16(void) /* Enable GPEs */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xec); reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xec, reg32); /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x114); |