- First stab at getting the ppc ports building and working.

- The sandpointx3+altimus has been consolidated into one directory for now.
- Added support for having different versions of the pci access functions
  on a per bus basis if needed.
  Hopefully I have not broken something inadvertently.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

12 files changed, 122 insertions, 36 deletions

diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 85f8fe4e86..464e66c51f 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -657,6 +657,7 @@ static struct device_operations pci_domain_ops = {
 	.enable_resources = enable_childrens_resources,
 	.init             = 0,
 	.scan_bus         = pci_domain_scan_bus,
+	.ops_pci_bus      = &pci_cf8_conf1,
 };
 
 static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
@@ -726,7 +727,6 @@ static void root_complex_enable_dev(struct device *dev)
 	/* Set the operations if it is a special bus type */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 		dev->ops = &pci_domain_ops;
-		pci_set_method_conf1();
 	}
 	else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 		dev->ops = &cpu_bus_ops;
diff --git a/src/northbridge/emulation/qemu-i386/northbridge.c b/src/northbridge/emulation/qemu-i386/northbridge.c
index 0a8ed5c1d8..dd120e29a5 100644
--- a/src/northbridge/emulation/qemu-i386/northbridge.c
+++ b/src/northbridge/emulation/qemu-i386/northbridge.c
@@ -115,7 +115,7 @@ static void enable_dev(struct device *dev)
 	/* Set the operations if it is a special bus type */
 	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 		dev->ops = &pci_domain_ops;
-		pci_set_method();
+		pci_set_method(dev);
 	}
 }
 
diff --git a/src/northbridge/ibm/cpc710/Config.lb b/src/northbridge/ibm/cpc710/Config.lb
index 8d8a895bd7..054a4c3997 100644
--- a/src/northbridge/ibm/cpc710/Config.lb
+++ b/src/northbridge/ibm/cpc710/Config.lb
@@ -2,10 +2,13 @@
 # Config file for IBM CPC710
 #
 
+config chip.h
+
 initobject cpc710.o
 initobject cpc710_pci.o
 #initobject cpc710_sdram.o
 
 object cpc710.o
 object cpc710_pci.o
-object cpc710_sdram.o
+#object cpc710_sdram.o
+driver cpc710_northbridge.o
diff --git a/src/northbridge/ibm/cpc710/chip.h b/src/northbridge/ibm/cpc710/chip.h
new file mode 100644
index 0000000000..e2b2ed5eaa
--- /dev/null
+++ b/src/northbridge/ibm/cpc710/chip.h
@@ -0,0 +1,6 @@
+
+struct northbridge_ibm_cpc710_config {
+	/* Nothing yet */
+};
+
+extern struct chip_operations northbridge_ibm_cpc710_ops;
diff --git a/src/northbridge/ibm/cpc710/cpc710_northbridge.c b/src/northbridge/ibm/cpc710/cpc710_northbridge.c
new file mode 100644
index 0000000000..2633dcd02c
--- /dev/null
+++ b/src/northbridge/ibm/cpc710/cpc710_northbridge.c
@@ -0,0 +1,103 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include "chip.h"
+
+static void pci_domain_read_resources(device_t dev)
+{
+	struct resource *resource;
+
+	/* Initialize the system wide io space constraints */
+	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	resource->base	= 0;
+	resource->limit = 0xffffUL;
+	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+	/* Initialize the system wide memory resources constraints */
+	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	resource->base	= 0x80000000ULL;
+	resource->limit = 0xfeffffffULL; /* We can put pci resources in the system controll area */
+	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+}
+
+static void ram_resource(device_t dev, unsigned long index,
+	unsigned long basek, unsigned long sizek)
+{
+	struct resource *resource;
+
+	if (!sizek) {
+		return;
+	}
+	resource = new_resource(dev, index);
+	resource->base	= ((resource_t)basek) << 10;
+	resource->size	= ((resource_t)sizek) << 10;
+	resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
+		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
+static void pci_domain_set_resources(device_t dev)
+{
+	int idx;
+
+	/* Report the memory regions */
+	idx = 10;
+	ram_resource(dev, idx++, 0, 1024*1024); /* FIXME */
+
+	/* And assign the resources */
+	assign_resources(&dev->link[0]);
+}
+
+
+static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+{
+	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+	return max;
+}
+
+static struct device_operations pci_domain_ops = {
+	.read_resources	  = pci_domain_read_resources,
+	.set_resources	  = pci_domain_set_resources,
+	.enable_resources = enable_childrens_resources,
+	.init		  = 0,
+	.scan_bus	  = pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_ppc_conf1,
+};  
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(&dev->link[0]);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static struct device_operations cpu_bus_ops = {
+	.read_resources	  = cpu_bus_noop,
+	.set_resources	  = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init		  = cpu_bus_init,
+	.scan_bus	  = 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	}
+	else if (dev->path.type == DEVICE_PATH_CPU_BUS) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_ibm_cpc710_ops = {
+	CHIP_NAME("CPC710")
+	.enable_dev = enable_dev,
+};
diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index 6140c3f051..800831de3e 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -8,8 +8,6 @@
 #include <bitops.h>
 #include "chip.h"
 
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
 static void pci_domain_read_resources(device_t dev)
 {
         struct resource *resource;
@@ -67,7 +65,6 @@ static uint32_t find_pci_tolm(struct bus *bus)
 
 static void pci_domain_set_resources(device_t dev)
 {
-        struct resource *resource, *last;
 	device_t mc_dev;
         uint32_t pci_tolm;
 
@@ -157,6 +154,7 @@ static struct device_operations pci_domain_ops = {
         .enable_resources = enable_childrens_resources,
         .init             = 0,
         .scan_bus         = pci_domain_scan_bus,
+	.ops_pci_bus      = &pci_cf8_conf1,
 };  
 
 static void cpu_bus_init(device_t dev)
@@ -181,7 +179,6 @@ static void enable_dev(struct device *dev)
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
                 dev->ops = &pci_domain_ops;
-		pci_set_method_conf1();
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
                 dev->ops = &cpu_bus_ops;
diff --git a/src/northbridge/intel/i855pm/northbridge.c b/src/northbridge/intel/i855pm/northbridge.c
index c311a05edc..e612cf1efc 100644
--- a/src/northbridge/intel/i855pm/northbridge.c
+++ b/src/northbridge/intel/i855pm/northbridge.c
@@ -149,7 +149,7 @@ static void enable_dev(struct device *dev)
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
                 dev->ops = &pci_domain_ops;
-		pci_set_method();
+		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
                 dev->ops = &cpu_bus_ops;
diff --git a/src/northbridge/motorola/mpc107/Config.lb b/src/northbridge/motorola/mpc107/Config.lb
index c5eb4256ac..78fc99e85f 100644
--- a/src/northbridge/motorola/mpc107/Config.lb
+++ b/src/northbridge/motorola/mpc107/Config.lb
@@ -2,10 +2,9 @@
 # Objects linked with linuxbios
 #
 
+config chip.h
 # We need sdram_init() in ppc_main()
 initobject meminfo.o
 initobject mpc107.o
 
-# We need sizeram() in hardwaremain()
-object meminfo.o
-object mpc107.o
+object mpc107_northbridge.c
diff --git a/src/northbridge/motorola/mpc107/mpc107.c b/src/northbridge/motorola/mpc107/mpc107.c
index e7e75b9af5..ec91a675d7 100644
--- a/src/northbridge/motorola/mpc107/mpc107.c
+++ b/src/northbridge/motorola/mpc107/mpc107.c
@@ -25,7 +25,6 @@
 #include <arch/pciconf.h>
 #include <timer.h>
 #include <clock.h>
-#include <mem.h>
 #include "i2c.h"
 #include "mpc107.h"
 
@@ -45,27 +44,6 @@ memory_init(void)
 	(void)mpc107_config_memory(NUM_BANKS, banks, 2);
 }
 
-struct mem_range *
-sizeram(void)
-{
-	int i;
-	struct sdram_dimm_info dimms[NUM_DIMMS];
-	struct sdram_bank_info banks[NUM_BANKS];
-	static struct mem_range meminfo;
-
-	meminfo.basek = 0;
-	meminfo.sizek = 0;
-
-	mpc107_probe_dimms(NUM_DIMMS, dimms, banks);
-
-	for (i = 0; i < NUM_BANKS; i++)
-		meminfo.sizek += banks[i].size;
-
-	meminfo.sizek >>= 10;
-
-	return &meminfo;
-}
-
 /*
  * Configure the MPC107 with the most pessimistic settings. These
  * are modified by reading the SPD EEPROM and adjusting accordingly.
diff --git a/src/northbridge/transmeta/tm5800/northbridge.c b/src/northbridge/transmeta/tm5800/northbridge.c
index 8a85a9e704..5ee97393e9 100644
--- a/src/northbridge/transmeta/tm5800/northbridge.c
+++ b/src/northbridge/transmeta/tm5800/northbridge.c
@@ -142,7 +142,7 @@ static void enable_dev(struct device *dev)
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
                 dev->ops = &pci_domain_ops;
-		pci_set_method();
+		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
                 dev->ops = &cpu_bus_ops;
diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index 4daedc5f3e..b578a975e4 100644
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -186,7 +186,7 @@ static void enable_dev(struct device *dev)
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
                 dev->ops = &pci_domain_ops;
-		pci_set_method();
+		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
                 dev->ops = &cpu_bus_ops;
diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
index 94880b9102..77c03d0bc8 100644
--- a/src/northbridge/via/vt8623/northbridge.c
+++ b/src/northbridge/via/vt8623/northbridge.c
@@ -268,7 +268,7 @@ static void enable_dev(struct device *dev)
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
                 dev->ops = &pci_domain_ops;
-		pci_set_method();
+		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
                 dev->ops = &cpu_bus_ops;