diff options
| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2011-02-28 00:10:37 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-02-28 00:10:37 +0000 |
| commit | adb23a51f5f711d10798a0bcddf4764a5dc0ae7c (patch) | |
| tree | bdd085f43754f7d1e54a429a30c8a8557b63451c /src/northbridge | |
| parent | 1f4fffb9ccaa3d145b66ddc3e57109cfe8f9fef7 (diff) | |
| download | coreboot-adb23a51f5f711d10798a0bcddf4764a5dc0ae7c.tar.xz | |
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Bring F3xD4 (Clock/Power Control Register 0) more in line
with BKDG i more cases. It requires looking at the CPU package type
so I add a function for that (in the wrong place?) and some
new constants
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdfam10/raminit_amdmct.c | 5 | ||||
| -rw-r--r-- | src/northbridge/amd/amdht/AsPsDefs.h | 6 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/amddefs.h | 10 |
3 files changed, 21 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 61a6c0f4cd..352d90acf1 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -214,6 +214,11 @@ u32 mctGetLogicalCPUID(u32 Node) return ret; } +static u8 mctGetProcessorPackageType(void) { + /* FIXME: I guess this belongs wherever mctGetLogicalCPUID ends up ? */ + u32 BrandId = cpuid_ebx(0x80000001); + return (u8)((BrandId >> 28) & 0x0F); +} static void raminit_amdmct(struct sys_info *sysinfo) { diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index a0d8c665b7..7e102790ab 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -111,6 +111,7 @@ #define NB_FID_EN 0x20 /* NbFidEn bit ON */ #define NB_CLKDID_ALL 0x80000000 /* NbClkDidApplyAll bit ON */ #define NB_CLKDID 0x40000000 /* NbClkDid value set by BIOS */ +#define NB_CLKDID_SHIFT 28 /* NbClkDid bit shift */ #define PW_STP_UP50 0x08000000 /* PowerStepUp 50nS(1000b) */ #define PW_STP_DN50 0x00800000 /* PowerStepDown 50nS (1000b)*/ #define PW_STP_UP100 0x03000000 /* PowerStepUp 100nS(0011b) */ @@ -119,6 +120,11 @@ #define PW_STP_DN200 0x00200000 /* PowerStepDown 200nS (0010b)*/ #define PW_STP_UP400 0x00000000 /* PowerStepUp 400nS(0000b) */ #define PW_STP_DN400 0x00000000 /* PowerStepDown 400nS (0000b)*/ +#define CLK_RAMP_HYST_SEL_VAL 0x00000f00 /* value mask for clock ramp + hysteresis select. BIOS + should program + F3xC4[ClkRampHystSel] to + 1111b */ #define LNK_PLL_LOCK 0x00010000 /* LnkPllLock value set (01b) by BIOS */ diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 2d0a12e089..997100bc8f 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -134,3 +134,13 @@ #define DC_CFG 0xC0011022 #define BU_CFG 0xC0011023 #define BU_CFG2 0xC001102A + +/* + * Processor package types + */ +#define AMD_PKGTYPE_FrX_1207 0 +#define AMD_PKGTYPE_AM3_2r2 1 +#define AMD_PKGTYPE_S1gX 2 +#define AMD_PKGTYPE_G34 3 +#define AMD_PKGTYPE_ASB2 4 +#define AMD_PKGTYPE_C32 5 |