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authorArthur Heymans <arthur@aheymans.xyz>2019-11-12 23:48:42 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-15 16:46:18 +0000
commitc583920a748fb8bd7999142433ad08641b06283d (patch)
treeac67268b34fed71bbf5f2915e6da0860151e60ee /src/northbridge
parente27c013f39f0433dac57a754b3484553a536f30d (diff)
downloadcoreboot-c583920a748fb8bd7999142433ad08641b06283d.tar.xz
nb/intel/i945: Initialize console in bootblock
Change-Id: Ic6ea158714998195614a63ee46a057f405de5616 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i945/Kconfig1
-rw-r--r--src/northbridge/intel/i945/i945.h2
-rw-r--r--src/northbridge/intel/i945/romstage.c9
3 files changed, 0 insertions, 12 deletions
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 5aa004d9eb..a0550ec3c7 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -28,7 +28,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select PARALLEL_MP
select C_ENVIRONMENT_BOOTBLOCK
- select NO_BOOTBLOCK_CONSOLE
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index e9e6f4d094..82f80ff725 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -378,8 +378,6 @@ u32 decode_tseg_size(const u8 esmramc);
/* Romstage mainboard callbacks */
/* Optional: Override the default LPC config. */
void mainboard_lpc_decode(void);
-/* Optional: Initialize the superio for serial output. */
-void mainboard_superio_config(void);
/* Optional: mainboard specific init after console init and before raminit. */
void mainboard_pre_raminit_config(int s3_resume);
/* Mainboard specific RCBA init. Happens after raminit. */
diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c
index c11a78ab0e..479588129d 100644
--- a/src/northbridge/intel/i945/romstage.c
+++ b/src/northbridge/intel/i945/romstage.c
@@ -28,10 +28,6 @@ __weak void mainboard_lpc_decode(void)
{
}
-__weak void mainboard_superio_config(void)
-{
-}
-
__weak void mainboard_pre_raminit_config(int s3_resume)
{
}
@@ -51,12 +47,7 @@ void mainboard_romstage_entry(void)
enable_lapic();
- i82801gx_lpc_setup();
mainboard_lpc_decode();
- mainboard_superio_config();
-
- /* Set up the console */
- console_init();
if (MCHBAR16(SSKPD) == 0xCAFE) {
system_reset();