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author | Raul E Rangel <rrangel@chromium.org> | 2019-01-24 11:52:20 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-28 13:35:44 +0000 |
commit | df3064227fb252ccf0ffac6419910bdd6f6ec536 (patch) | |
tree | 76eb1e574ff3174611bd338e9abaa54482f5c5be /src/northbridge | |
parent | 595202c304d14e17b1ea1514169346d7cc637206 (diff) | |
download | coreboot-df3064227fb252ccf0ffac6419910bdd6f6ec536.tar.xz |
amd/stoneyridge: Disable GPIO MASK STATUS
MASK_STATUS disables interrupt status generation for the entire GPIO
controller when any debounce register is configured. This causes
problems when the kernel is loading drivers because we could lose
interrupts for previously loaded devices.
sb_program_gpios is also not setup to wait when configuring
PAD_DEBOUNCE, so there is a potential that we could lose the interrupt
status enable bit for other registers. By disabling MASK_STATUS we avoid
that problem.
BUG=b:113880780
BRANCH=none
TEST=Ran a reboot stress test that concluded that we are no longer
losing TPM interrupts while booting.
Change-Id: Ife1db3b1449f205092509595cbc3eca511bff57a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Diffstat (limited to 'src/northbridge')
0 files changed, 0 insertions, 0 deletions