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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-09 22:03:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-07 06:41:47 +0000 |
| commit | e07df9d78351cda0818309fc7f3e78d8057d421e (patch) | |
| tree | 616c616cfa71664b43bee0ceab9749481637fdc9 /src/northbridge | |
| parent | a16cffe480f0e4ce8da28e2893d27f012963ab5a (diff) | |
| download | coreboot-e07df9d78351cda0818309fc7f3e78d8057d421e.tar.xz | |
nb/intel/i945: Enable and allocate 8M for TSEG
TSEG can be used as a stage cache and SMM can be relocated here.
Tested on Intel D945GCLF, still boots.
Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25592
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index bf486a0aaf..7de2c73fc9 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -192,6 +192,11 @@ static void i945_setup_bars(void) gfxsize = 2; pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4)); + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + reg8 &= ~0x7; + reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */ + pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8); + /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |