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authorGreg Watson <jarrah@users.sourceforge.net>2004-11-22 21:36:46 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2004-11-22 21:36:46 +0000
commite5c0ca30a2c57f7cf841c49fd29e87f4eea9bde1 (patch)
treefcbfb224a49b1d6aaded7f3a3ef26cb05f8df5a9 /src/northbridge
parentabc4a11a9a4de69d77d9f74d0026ca149c9583f6 (diff)
downloadcoreboot-e5c0ca30a2c57f7cf841c49fd29e87f4eea9bde1.tar.xz
pci_read using wrong device
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/motorola/mpc107/mpc107_northbridge.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/northbridge/motorola/mpc107/mpc107_northbridge.c b/src/northbridge/motorola/mpc107/mpc107_northbridge.c
index ee9a5e2aee..fec70b0f8c 100644
--- a/src/northbridge/motorola/mpc107/mpc107_northbridge.c
+++ b/src/northbridge/motorola/mpc107/mpc107_northbridge.c
@@ -41,15 +41,15 @@ static void pci_domain_set_resources(device_t dev)
unsigned long start, end, size;
/* Find the memory setup */
- memstart1 = pci_read_config32(dev, 0x80);
- memstart2 = pci_read_config32(dev, 0x84);
- extmemstart1 = pci_read_config32(dev, 0x88);
- extmemstart1 = pci_read_config32(dev, 0x8c);
- memend1 = pci_read_config32(dev, 0x90);
- memend2 = pci_read_config32(dev, 0x94);
- extmemend1 = pci_read_config32(dev, 0x98);
- extmemend2 = pci_read_config32(dev, 0x9c);
- bank_enable = pci_read_config32(dev, 0xa0);
+ memstart1 = pci_read_config32(mc_dev, 0x80);
+ memstart2 = pci_read_config32(mc_dev, 0x84);
+ extmemstart1 = pci_read_config32(mc_dev, 0x88);
+ extmemstart1 = pci_read_config32(mc_dev, 0x8c);
+ memend1 = pci_read_config32(mc_dev, 0x90);
+ memend2 = pci_read_config32(mc_dev, 0x94);
+ extmemend1 = pci_read_config32(mc_dev, 0x98);
+ extmemend2 = pci_read_config32(mc_dev, 0x9c);
+ bank_enable = pci_read_config32(mc_dev, 0xa0);
/* Report the memory regions */
idx = 10;