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| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-20 18:03:27 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-22 11:43:16 +0000 |
| commit | eb86016570d0f7dde331d6df531f386bff590fb1 (patch) | |
| tree | 7aad9fe7137b91ed12c29953a06c0dd8c874198d /src/northbridge | |
| parent | 645d2a817ab98c75230b1253749746467eacf220 (diff) | |
| download | coreboot-eb86016570d0f7dde331d6df531f386bff590fb1.tar.xz | |
nb/intel/haswell: Use 16-bit ops on PCI COMMAND
The PCI COMMAND register is 16 bits wide. So, do not use 32-bit PCI ops
to update it.
Change-Id: I8f8d9e978f3b241cb544dd1d26e0f5fa8997d11e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/minihd.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index c6b5a1257c..de2ce06410 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -59,7 +59,7 @@ static void minihd_init(struct device *dev) printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); /* Set Bus Master */ - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Mini-HD configuration */ reg32 = read32(base + 0x100c); |