diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-01-08 22:15:53 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-01-10 09:53:51 +0000 |
| commit | f5a57a883b6586c0e6dce9e6e34add09a96e647e (patch) | |
| tree | 6b8cd82b302fe2d785c2f76a267f4e8e9c47f078 /src/northbridge | |
| parent | ab4eb2afc34266b53c6201bbca907dcb2ff07410 (diff) | |
| download | coreboot-f5a57a883b6586c0e6dce9e6e34add09a96e647e.tar.xz | |
mb: Move timestamp_add_now to northbridge x4x
Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index b3b84d8061..d9fa49d9da 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -22,6 +22,7 @@ #include <arch/cpu.h> #include <delay.h> #include <halt.h> +#include <lib.h> #include "iomap.h" #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ @@ -34,6 +35,7 @@ #include <device/dram/ddr2.h> #include <device/dram/ddr3.h> #include <mrc_cache.h> +#include <timestamp.h> #define MRC_CACHE_VERSION 0 @@ -639,6 +641,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map) int fast_boot, cbmem_was_inited, cache_not_found; struct region_device rdev; + timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); pci_write_config8(PCI_DEV(0, 0, 0), 0xdf, 0xff); @@ -728,4 +731,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map) outb(0x6, 0xcf9); halt(); } + + timestamp_add_now(TS_AFTER_INITRAM); + quick_ram_check(); + printk(BIOS_DEBUG, "Memory initialized\n"); } |