diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-27 20:14:59 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-16 09:50:51 +0000 |
commit | f765d4f275197cfa791d70b2236b7273e4a70c53 (patch) | |
tree | 1465c4b68585309769d25561c4c2a6b66cae9055 /src/northbridge | |
parent | e9a0130879bca97462c6184f1d368f773e00e8a0 (diff) | |
download | coreboot-f765d4f275197cfa791d70b2236b7273e4a70c53.tar.xz |
src: Remove unneeded include <lib.h>
Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r-- | src/northbridge/amd/amdfam10/link_control.c | 1 | ||||
-rw-r--r-- | src/northbridge/amd/amdfam10/nb_control.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/i945/debug.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/x4x/raminit.c | 1 | ||||
-rw-r--r-- | src/northbridge/via/vx900/northbridge.c | 1 |
6 files changed, 0 insertions, 6 deletions
diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c index a7fbe4cd7b..f82f238bc0 100644 --- a/src/northbridge/amd/amdfam10/link_control.c +++ b/src/northbridge/amd/amdfam10/link_control.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> -#include <lib.h> #include <cpu/amd/model_10xxx_rev.h> #include "amdfam10.h" diff --git a/src/northbridge/amd/amdfam10/nb_control.c b/src/northbridge/amd/amdfam10/nb_control.c index 1884799ec4..255948db87 100644 --- a/src/northbridge/amd/amdfam10/nb_control.c +++ b/src/northbridge/amd/amdfam10/nb_control.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> -#include <lib.h> #include <cpu/amd/model_10xxx_rev.h> #include "amdfam10.h" diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 0f388df4fb..ef4f17bc6d 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -15,7 +15,6 @@ */ #include <spd.h> -#include <lib.h> #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 63108de893..7345443c3d 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -19,7 +19,6 @@ #include <string.h> #include <console/console.h> #include <arch/io.h> -#include <lib.h> #include <cpu/x86/lapic.h> #include <timestamp.h> #include "sandybridge.h" diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index ce5c2ebcf0..c97c139031 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -22,7 +22,6 @@ #include <arch/cpu.h> #include <delay.h> #include <halt.h> -#include <lib.h> #include "iomap.h" #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index a699d86ed1..2b81b47ff2 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -24,7 +24,6 @@ #include <cpu/cpu.h> #include <cbmem.h> #include <cf9_reset.h> -#include <lib.h> #include <reset.h> #include <string.h> |