diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-19 11:04:28 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:12:51 +0000 |
| commit | 1146332b9c3a0a21424b72bf7e68f07eb370f60b (patch) | |
| tree | 047bea0d8a31e58b145adc7faa69b15d827a518c /src/northbridge | |
| parent | 08f749d5f6a4efd7f69ea56e70a231ceebacde09 (diff) | |
| download | coreboot-1146332b9c3a0a21424b72bf7e68f07eb370f60b.tar.xz | |
nb/intel/sandybridge: Increase tRWDRDD with fast RAM
This has been reported to increase stability, and vendor BIOS also does
the same.
Change-Id: I4e3ea76f61771683dea61b18bee531516cda5843
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 7e937862db..6ba91c96e3 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2778,6 +2778,9 @@ void prepare_training(ramctr_timing *ctrl) void set_read_write_timings(ramctr_timing *ctrl) { + /* Use a larger delay when running fast to improve stability */ + const u32 tRWDRDD_inc = ctrl->tCK <= TCK_1066MHZ ? 4 : 2; + int channel, slotrank; FOR_ALL_POPULATED_CHANNELS { @@ -2800,7 +2803,7 @@ void set_read_write_timings(ramctr_timing *ctrl) .tRRDD = val, .tWWDR = val, .tWWDD = val, - .tRWDRDD = ctrl->ref_card_offset[channel] + 2, + .tRWDRDD = ctrl->ref_card_offset[channel] + tRWDRDD_inc, .tWRDRDD = tWRDRDD, .tRWSR = 2, .dec_wrd = 1, |