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| author | Zheng Bao <zheng.bao@amd.com> | 2010-08-05 06:12:16 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2010-08-05 06:12:16 +0000 |
| commit | 23ffe8b6904187ecc4860f71794e995bd123704a (patch) | |
| tree | b1537127321567665532cdc5d750355a868c58fd /src/northbridge | |
| parent | 127e976ec287df4ceb16a3b176b58497e58e0d8d (diff) | |
| download | coreboot-23ffe8b6904187ecc4860f71794e995bd123704a.tar.xz | |
The number of cores is got by reading the bit 15,13,12 of [0,24,3,e8].
The bit 15 seems to be a new feature when CPU started to have more than 4
cores.
Zheng
Yes, this was add for revD.
Marc Jones
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdht/h3ncmn.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 5222e0f505..1fcb07d633 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -555,16 +555,17 @@ static u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) u8 i; ASSERT((node < nb->maxNodes)); - /* Read CmpCap */ + /* Read CmpCap [2][1:0] */ AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(node), makePCIBusFromNode(node), makePCIDeviceFromNode(node), CPU_NB_FUNC_03, REG_NB_CAPABILITY_3XE8), - 13, 12, &temp); + 15, 12, &temp); + /* bits[15,13,12] specify the cores */ /* Support Downcoring */ - cores = temp + 1; + cores = ((temp & 8) >> 1) + (temp & 3) + 1; AmdPCIReadBits (MAKE_SBDFO(makePCISegmentFromNode(node), makePCIBusFromNode(node), makePCIDeviceFromNode(node), |