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authorAngel Pons <th3fanbus@gmail.com>2020-06-08 12:38:19 +0200
committerFelix Held <felix-coreboot@felixheld.de>2020-06-10 01:52:51 +0000
commit26766fd85d87dcd328ca55c8a51a43222eca59f1 (patch)
treeb71e4751e3d2bd73a28300ed095cdb1be16dd12e /src/northbridge
parenta4098c759dca00ef47c821032a5effe572083645 (diff)
downloadcoreboot-26766fd85d87dcd328ca55c8a51a43222eca59f1.tar.xz
nb/intel/pineview: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change. Change-Id: Idd6a11e95669f0a8fe9bd52359a9822b524c878c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42192 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/pineview/early_init.c4
-rw-r--r--src/northbridge/intel/pineview/raminit.c13
2 files changed, 6 insertions, 11 deletions
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index 5b9ef4d3fd..42a68d8c02 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -62,8 +62,8 @@ static void early_graphics_setup(void)
pci_write_config16(GMCH_IGD, 0xcc, reg16);
- pci_write_config8(GMCH_IGD, 0x62, pci_read_config8(GMCH_IGD, 0x62) & ~0x3);
- pci_write_config8(GMCH_IGD, 0x62, pci_read_config8(GMCH_IGD, 0x62) | 2);
+ pci_and_config8(GMCH_IGD, 0x62, ~0x3);
+ pci_or_config8(GMCH_IGD, 0x62, 2);
if (config->use_crt) {
/* Enable VGA */
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 25c9ba2544..af846e3588 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -2152,8 +2152,7 @@ static void sdram_enhancedmode(struct sysinfo *s)
MCHBAR8_OR(C0CWBCTRL, 1);
MCHBAR16_OR(C0ARBSPL, 0x0100);
- reg8 = pci_read_config8(HOST_BRIDGE, 0xf0);
- pci_write_config8(HOST_BRIDGE, 0xf0, reg8 | 1);
+ pci_or_config8(HOST_BRIDGE, 0xf0, 1);
MCHBAR32(SBCTL) = 0x00000002;
MCHBAR32(SBCTL2) = 0x20310002;
MCHBAR32(SLIMCFGTMG) = 0x02020302;
@@ -2162,8 +2161,7 @@ static void sdram_enhancedmode(struct sysinfo *s)
MCHBAR32(HIT2) = 0x07000000;
MCHBAR32(HIT3) = 0x01014010;
MCHBAR32(HIT4) = 0x0f038000;
- reg8 = pci_read_config8(HOST_BRIDGE, 0xf0);
- pci_write_config8(HOST_BRIDGE, 0xf0, reg8 & ~1);
+ pci_and_config8(HOST_BRIDGE, 0xf0, ~1);
u32 nranks, curranksize, maxranksize, dra;
u8 rankmismatch;
@@ -2569,7 +2567,6 @@ static void sdram_programdqdqs(struct sysinfo *s)
void sdram_initialize(int boot_path, const u8 *spd_addresses)
{
struct sysinfo si;
- u8 reg8;
const char *boot_str[] = {"Normal", "Reset", "Resume"};
PRINTK_DEBUG("Setting up RAM controller.\n");
@@ -2685,12 +2682,10 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
MCHBAR32_OR(C0REFRCTRL2, 1 << 30);
/* Tell ICH7 that we're done */
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80);
+ pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7));
/* Tell northbridge we're done */
- reg8 = pci_read_config8(HOST_BRIDGE, 0xf4);
- pci_write_config8(HOST_BRIDGE, 0xf4, reg8 | 1);
+ pci_or_config8(HOST_BRIDGE, 0xf4, 1);
printk(BIOS_DEBUG, "RAM initialization finished.\n");
}