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authorArthur Heymans <arthur@aheymans.xyz>2019-10-23 17:25:58 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-11-01 11:44:51 +0000
commit340e4b80904feb6c5c21497fc52966854fa5ee79 (patch)
tree4026de0ec0cc41f51dd121a0be76642a8d0a286d /src/northbridge
parent44874482fec69a849b06c378aa3eb69e75425256 (diff)
downloadcoreboot-340e4b80904feb6c5c21497fc52966854fa5ee79.tar.xz
lib/cbmem_top: Add a common cbmem_top implementation
This adds a common cbmem_top implementation to all coreboot target. In romstage a static variable will be used to cache the result of cbmem_top_romstage. In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable needs to be populated by the stage entry with the value passed via the calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the same implementation as will be used as in romstage. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/e7505/memmap.c2
-rw-r--r--src/northbridge/intel/fsp_rangeley/memmap.c2
-rw-r--r--src/northbridge/intel/gm45/memmap.c2
-rw-r--r--src/northbridge/intel/haswell/memmap.c2
-rw-r--r--src/northbridge/intel/i440bx/memmap.c2
-rw-r--r--src/northbridge/intel/i945/memmap.c2
-rw-r--r--src/northbridge/intel/nehalem/memmap.c2
-rw-r--r--src/northbridge/intel/pineview/memmap.c2
-rw-r--r--src/northbridge/intel/sandybridge/memmap.c2
-rw-r--r--src/northbridge/intel/x4x/memmap.c2
-rw-r--r--src/northbridge/via/vx900/memmap.c2
11 files changed, 11 insertions, 11 deletions
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index c6a20fab9d..009db80215 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -21,7 +21,7 @@
#include <program_loading.h>
#include "e7505.h"
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
pci_devfn_t mch = PCI_DEV(0, 0, 0);
uintptr_t tolm;
diff --git a/src/northbridge/intel/fsp_rangeley/memmap.c b/src/northbridge/intel/fsp_rangeley/memmap.c
index da9ed71a67..275ddd3ac1 100644
--- a/src/northbridge/intel/fsp_rangeley/memmap.c
+++ b/src/northbridge/intel/fsp_rangeley/memmap.c
@@ -36,7 +36,7 @@ static uintptr_t smm_region_start(void)
return tom;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
}
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 7479a7834a..d34820eb3d 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -117,7 +117,7 @@ static size_t northbridge_get_tseg_size(void)
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
return (void *) top_of_ram;
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index 007a67d4b3..74d9292c14 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -34,7 +34,7 @@ static uintptr_t smm_region_start(void)
return tom & ~((1 << 20) - 1);
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *)smm_region_start();
}
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c
index 75a6c7e243..d260af6f32 100644
--- a/src/northbridge/intel/i440bx/memmap.c
+++ b/src/northbridge/intel/i440bx/memmap.c
@@ -23,7 +23,7 @@
#include <program_loading.h>
#include "i440bx.h"
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
/* Base of TSEG is top of usable DRAM */
/*
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 8207d06a55..000ac7e682 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -71,7 +71,7 @@ static size_t northbridge_get_tseg_size(void)
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
return (void *) top_of_ram;
diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c
index 1c17b0d9b5..5de4b80acf 100644
--- a/src/northbridge/intel/nehalem/memmap.c
+++ b/src/northbridge/intel/nehalem/memmap.c
@@ -42,7 +42,7 @@ static size_t northbridge_get_tseg_size(void)
return CONFIG_SMM_TSEG_SIZE;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *) smm_region_start();
}
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index b4fef6bc76..0aa70cdb34 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -132,7 +132,7 @@ static uintptr_t northbridge_get_tseg_base(void)
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
return (void *) top_of_ram;
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index 67de34459b..99888fa2ae 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -31,7 +31,7 @@ static uintptr_t smm_region_start(void)
return tom;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
return (void *) smm_region_start();
}
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 41e491200b..1924ddf678 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -128,7 +128,7 @@ static uintptr_t northbridge_get_tseg_base(void)
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
return (void *) top_of_ram;
diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c
index d11dc65fd6..3121d7406e 100644
--- a/src/northbridge/via/vx900/memmap.c
+++ b/src/northbridge/via/vx900/memmap.c
@@ -120,7 +120,7 @@ u32 vx900_get_tolm(void)
return (pci_read_config16(MCU, 0x84) & 0xfff0) >> 4;
}
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
{
uintptr_t tolm;
uintptr_t fb_size;