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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-09 11:41:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-15 05:32:44 +0000
commit544878b56349a74e8cb7a0e9af899b5f7fc246fc (patch)
tree0a586dcbe6e70c94be6b7d123f43dd7c294dad68 /src/northbridge
parent5bc641afebda5fd274ba713add4145651d9bc71d (diff)
downloadcoreboot-544878b56349a74e8cb7a0e9af899b5f7fc246fc.tar.xz
arch/x86: Add postcar_frame_common_mtrrs()
As most platforms will share the subset of enabling both low RAM WB and high ROM WP MTRRs, provide them with a single function. Add possibility for the platform to skip these if required. Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/e7505/memmap.c2
-rw-r--r--src/northbridge/intel/gm45/memmap.c7
-rw-r--r--src/northbridge/intel/haswell/memmap.c6
-rw-r--r--src/northbridge/intel/i440bx/memmap.c7
-rw-r--r--src/northbridge/intel/i945/memmap.c7
-rw-r--r--src/northbridge/intel/nehalem/memmap.c7
-rw-r--r--src/northbridge/intel/pineview/memmap.c7
-rw-r--r--src/northbridge/intel/sandybridge/memmap.c7
-rw-r--r--src/northbridge/intel/x4x/memmap.c7
9 files changed, 2 insertions, 55 deletions
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index c3b59e9415..7033f89a04 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -54,6 +54,8 @@ void fill_postcar_frame(struct postcar_frame *pcf)
* operations when source is left as UC.
*/
+ pcf->skip_common_mtrr = 1;
+
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 9337470e1e..71037aedd0 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -138,13 +138,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index 13881e99b2..f43bd2f3bc 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -57,12 +57,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c
index 084679ff4a..e4e5de7fc3 100644
--- a/src/northbridge/intel/i440bx/memmap.c
+++ b/src/northbridge/intel/i440bx/memmap.c
@@ -72,13 +72,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache CBMEM region as WB. */
top_of_ram = (uintptr_t)cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 5f3e2569fb..6092c25770 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -104,13 +104,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/
diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c
index 1a3a6d7cdf..031240c2f3 100644
--- a/src/northbridge/intel/nehalem/memmap.c
+++ b/src/northbridge/intel/nehalem/memmap.c
@@ -62,13 +62,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 66900af2ef..2e028892e3 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -154,13 +154,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index 99f11a0f2a..83a67abeb8 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -61,13 +61,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
top_of_ram = (uintptr_t)cbmem_top();
/* Cache 8MiB below the top of ram. On sandybridge systems the top of
* ram under 4GiB is the start of the TSEG region. It is required to
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 254ca880fa..a61d64e61d 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -149,13 +149,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
-
- /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/