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| author | Martin Roth <martinroth@google.com> | 2015-11-27 13:05:04 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-12-06 18:46:12 +0100 |
| commit | 7c38e1e8bc47c2842b23c565a35f8d959428ec3c (patch) | |
| tree | 8c85b6227ae2d72c37f77cc68483778bb34e450b /src/northbridge | |
| parent | 19fbdcc8283e0e499cb517d1149225bfadc61f03 (diff) | |
| download | coreboot-7c38e1e8bc47c2842b23c565a35f8d959428ec3c.tar.xz | |
Remove #ifdef checks on Kconfig symbols
In coreboot, bool, hex, and int type symbols are ALWAYS defined.
Change-Id: I58a36b37075988bb5ff67ac692c7d93c145b0dbc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12560
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdk8/coherent_ht.c | 9 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 4 |
2 files changed, 0 insertions, 13 deletions
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 6554e075ea..8779ec7c7b 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -93,10 +93,6 @@ #define TRY_HIGH_FIRST 0 #endif -#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT - #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0 -#endif - #ifndef K8_HT_CHECK_PENDING_LINK #if CONFIG_MAX_PHYSICAL_CPUS >= 4 #define K8_HT_CHECK_PENDING_LINK 1 @@ -109,11 +105,6 @@ #define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0 #endif -#ifndef CONFIG_ENABLE_APIC_EXT_ID - #define CONFIG_ENABLE_APIC_EXT_ID 0 -#endif - - static inline void print_linkn (const char *strval, uint8_t byteval) { printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index f63e0e69f9..08c3b0cf42 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -24,10 +24,6 @@ #include "../chip.h" #include <reset.h> -#ifndef CONFIG_ENABLE_FSP_FAST_BOOT -# error "CONFIG_ENABLE_FSP_FAST_BOOT must be set." -#endif - #ifdef __PRE_RAM__ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) |