diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 15:18:38 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-23 14:49:57 +0000 |
| commit | 84fdda381224f0371e27ef3f0ad77ee1103cb05a (patch) | |
| tree | 08aa40dd49e214fe0fd05b7960ba3b3c00e55ccb /src/northbridge | |
| parent | c82950bf79285fa838b6fbaf019a5638316ba053 (diff) | |
| download | coreboot-84fdda381224f0371e27ef3f0ad77ee1103cb05a.tar.xz | |
nb/intel/pineview: Use parallel MP init
Remove guards around CPU code on which all platforms use parallel MP
init code.
This removes the option to disable HT siblings.
Tested on Foxconn D41S.
Change-Id: I89f7d514d75fe933c3a8858da37004419189674b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25602
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/pineview/Kconfig | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/northbridge.c | 22 |
2 files changed, 2 insertions, 21 deletions
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 6168305f7a..b5925012a3 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -31,6 +31,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select POSTCAR_STAGE select POSTCAR_CONSOLE select SMM_TSEG + select PARALLEL_MP config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index ee1efd3b1e..ec2c902b90 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -151,26 +151,6 @@ void northbridge_write_smram(u8 smram) pci_write_config8(dev, SMRAM, smram); } -/* - * Really doesn't belong here but will go away with parallel mp init, - * so let it be here for a while... - */ -int cpu_get_apic_id_map(int *apic_id_map) -{ - unsigned int i; - - /* Logical processors (threads) per core */ - const struct cpuid_result cpuid1 = cpuid(1); - /* Read number of cores. */ - const char cores = (cpuid1.ebx >> 16) & 0xf; - - /* TODO in parallel MP cpuid(1).ebx */ - for (i = 0; i < cores; i++) - apic_id_map[i] = i; - - return cores; -} - static void mch_domain_set_resources(struct device *dev) { struct resource *res; @@ -218,7 +198,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(struct device *dev) { - initialize_cpus(dev->link_list); + bsp_init_and_start_aps(dev->link_list); } static struct device_operations cpu_bus_ops = { |