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authorIndrek Kruusa <indrek.kruusa@artecdesign.ee>2006-08-03 16:48:18 +0000
committerStefan Reinauer <stepan@openbios.org>2006-08-03 16:48:18 +0000
commit8e3464109e47945b1a4d7e3dd0c6e291593de70a (patch)
tree03493e297dc332c8c7613303eb874e12830e0a5a /src/northbridge
parent8ad7c06535694959952b7d64a9649cb9534abd2a (diff)
downloadcoreboot-8e3464109e47945b1a4d7e3dd0c6e291593de70a.tar.xz
Changelog:
* src/cpu/amd/model_lx/model_lx_init.c L2 cache initialization removed (moved to northbridge.c) * src/include/cpu/amd/lxdef.h more checked values * src/northbridge/amd/lx/northbridge.c L2 cache initialization added cpubug() commented out * src/northbridge/amd/lx/raminit.c empty function sdram_set_registers() is in use, don't remove * src/mainboard/artecgroup/dbe61/Config.lb irqmap changes * src/mainboard/artecgroup/dbe61/irq_tables.c tentative changes to irq table (currently not in use) * src/mainboard/artecgroup/dbe61/mainboard.c irq assigned manually to NIC * src/mainboard/artecgroup/dbe61/Options.lb gcc 4.0 is OK * targets/artecgroup/dbe61/Config.lb 64K for VSA is OK at moment Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/lx/northbridge.c36
-rw-r--r--src/northbridge/amd/lx/raminit.c5
2 files changed, 36 insertions, 5 deletions
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 2de9afc7b6..14617243dd 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -9,6 +9,7 @@
#include <bitops.h>
#include "chip.h"
#include "northbridge.h"
+#include <cpu/cpu.h>
#include <cpu/amd/lxdef.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
@@ -274,6 +275,38 @@ static void enable_shadow(device_t dev)
}
+
+static void enable_L2_cache(void) {
+ msr_t msr;
+
+ /* Instruction Memory Configuration register
+ * set EBE bit, required when L2 cache is enabled
+ */
+ msr = rdmsr(CPU_IM_CONFIG);
+ msr.lo |= 0x400;
+ wrmsr(CPU_IM_CONFIG, msr);
+
+ /* Data Memory Subsystem Configuration register
+ * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
+ */
+ msr = rdmsr(CPU_DM_CONFIG0);
+ msr.lo |= 0x4000;
+ wrmsr(CPU_DM_CONFIG0, msr);
+
+ /* invalidate L2 cache */
+ msr.hi = 0x00;
+ msr.lo = 0x10;
+ wrmsr(L2_CONFIG_MSR, msr);
+
+ /* Enable L2 cache */
+ msr.hi = 0x00;
+ msr.lo = 0x0f;
+ wrmsr(L2_CONFIG_MSR, msr);
+
+ printk_debug("L2 cache enabled\n");
+}
+
+
static void northbridge_init(device_t dev)
{
struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;
@@ -456,8 +489,9 @@ static void enable_dev(struct device *dev)
extern void cpubug(void);
printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
/* cpubug MUST be called before setup_lx(), so we force the issue here */
+ enable_L2_cache();
northbridgeinit();
- cpubug();
+ /* cpubug(); GX3*/
chipsetinit(nb);
setup_lx();
/* do this here for now -- this chip really breaks our device model */
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 7fd39ae22e..d4a5d7b701 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -1,13 +1,10 @@
#include <cpu/amd/lxdef.h>
-#if 0
+
static void sdram_set_registers(const struct mem_controller *ctrl)
{
}
-#endif
-
-
/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
static void sdram_enable(int controllers, const struct mem_controller *ctrl)