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| author | Aaron Durbin <adurbin@chromium.org> | 2014-08-19 15:34:51 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-27 08:03:27 +0100 |
| commit | 913067d44f4daa2d58aacac0c33cb2938a0b3740 (patch) | |
| tree | 43c9f4d65aa39ba26e7af274cfba2820bac923c8 /src/northbridge | |
| parent | 9edf38ef1f366f10f1878cec34918934faf12dac (diff) | |
| download | coreboot-913067d44f4daa2d58aacac0c33cb2938a0b3740.tar.xz | |
tegra132: initialize GIC
This provides are barebones initialization for tegra132 GIC
on CPU0. It routes all interrupts to CPU0, moves them all
into group 1, and attempts to allow non-secure access for
all registers (doesn't appear to be implemented, though).
BUG=chrome-os-partner:31449
BRANCH=None
TEST=Built and booted past smp init in the kernel. Timers
appear to be flowing now since jiffies are updated.
Change-Id: Id45c13cc23e50feed3d88da13420c9eb694498a0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 81bad0a53083baa7af0f1fd5f82fef0538ee62df
Original-Change-Id: I69dd9ae53f259e876a9bc4b9d7f65330150d2990
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212795
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8995
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge')
0 files changed, 0 insertions, 0 deletions