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authorKeith Hui <buurin@gmail.com>2010-03-13 20:16:48 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-03-13 20:16:48 +0000
commit9c1e1f0d3a562d6f1fb1a1bad5a8f58f62bf4613 (patch)
tree6de7fe916008931e6b9ed253a30849fd5ca11ebd /src/northbridge
parentf7f9e92b4235169974c8f314ff6a921a0b7c4f9e (diff)
downloadcoreboot-9c1e1f0d3a562d6f1fb1a1bad5a8f58f62bf4613.tar.xz
Add SDRAMPWR_4DIMM Kconfig option (not user-visible in menuconfig).
Each Intel 440BX board should select this option if it has 4 DIMM slots on the PCB, and _not_ select it (it defaults to 'n') if it has 3 DIMMs on the PCB. Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i440bx/Kconfig13
-rw-r--r--src/northbridge/intel/i440bx/raminit.c6
2 files changed, 18 insertions, 1 deletions
diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
index 696e884705..4de84d3472 100644
--- a/src/northbridge/intel/i440bx/Kconfig
+++ b/src/northbridge/intel/i440bx/Kconfig
@@ -22,3 +22,16 @@ config NORTHBRIDGE_INTEL_I440BX
bool
select HAVE_HIGH_TABLES
+config SDRAMPWR_4DIMM
+ bool
+ depends on NORTHBRIDGE_INTEL_I440BX
+ default n
+ help
+ This option affects how the SDRAMC register is programmed.
+ Memory clock signals will not be routed properly if this option
+ is set wrong.
+
+ If your board has 4 DIMM slots, you must use select this option, in
+ your Kconfig file of the board. On boards with 3 DIMM slots,
+ do _not_ select this option.
+
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 3de2dd7021..43e2a45e99 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -292,7 +292,11 @@ static const long register_values[] = {
* 0 = 3 clocks of RAS# precharge
* 1 = 2 clocks of RAS# precharge
*/
- SDRAMC + 0, 0x00, 0x00,
+#if CONFIG_SDRAMPWR_4DIMM
+ SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */
+#else
+ SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots.*/
+#endif
SDRAMC + 1, 0x00, 0x00,
/* PGPOL - Paging Policy Register