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| author | Rudolf Marek <r.marek@assembler.cz> | 2010-08-17 21:03:17 +0000 |
|---|---|---|
| committer | Rudolf Marek <r.marek@assembler.cz> | 2010-08-17 21:03:17 +0000 |
| commit | c7d2773e121637b5b76d1437fac5a93e397a64bb (patch) | |
| tree | 4edd18fa390fe5c4917e28ab2af2aa0f5a646bb9 /src/northbridge | |
| parent | da71ba528406cadea6e83b30dd3448cc53e482f4 (diff) | |
| download | coreboot-c7d2773e121637b5b76d1437fac5a93e397a64bb.tar.xz | |
Attached patch removes unnecessary IRQ routing info (for ACPI, mptable etc needs to be fixed too). The devicetree.cb changes should reflect now the real board configuration. It has one 16x slot and 1x slot (GPP device 9) and GPP device a is onboard ethernet. The mainboard.c now presents the board name and
I removed the gpio asserts - I think those are not used here.
The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better.
The classic PCI slot works fine too. However it seems SATA has some issues.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
0 files changed, 0 insertions, 0 deletions