diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-08-27 13:18:53 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-29 19:37:08 +0100 |
| commit | df499b53c3ce8acbb4c303b2041d09cb526e252e (patch) | |
| tree | 5f434c6aa4bd5653d24459958759fd7cb9707a3e /src/northbridge | |
| parent | 0eb163d5d37bd497dcb0a9b8e0c40404617c8af7 (diff) | |
| download | coreboot-df499b53c3ce8acbb4c303b2041d09cb526e252e.tar.xz | |
nb/amd/amdmct/mct_ddr3: Fix a minor RDIMM CS select error
Change-Id: I4cdfeec887813c17edcdee8858222414fb19b72c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12057
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c index 01061a7335..a63fe2e552 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c @@ -232,7 +232,7 @@ void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat, for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel ++, MrsChipSel ++) { if (pDCTstat->CSPresent & (1 << MrsChipSel)) { val = Get_NB32_DCT(dev, dct, 0xa8); - val &= ~(0xf << 8); + val &= ~(0xff << 8); switch (MrsChipSel) { case 0: @@ -279,7 +279,7 @@ void FreqChgCtrlWrd(struct MCTStatStruc *pMCTstat, /* 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. */ val = Get_NB32_DCT(dev, dct, 0xa8); val &= ~(0xff << 8); - val |= (0x3 << (MrsChipSel & 0xfe)) << 8; + val |= (0x3 << (MrsChipSel & ~0x1)) << 8; Set_NB32_DCT(dev, dct, 0xa8, val); /* Resend control word 10 */ |