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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-07-11 10:40:45 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-11-14 05:38:17 +0100 |
| commit | e8179b51380cf0922466c33a9a0998a65f246a84 (patch) | |
| tree | 7b8294036e61fb45713214fb0cddcc671fa068fc /src/northbridge | |
| parent | 53508fedf8bbd49b10f39a18b3bad6b25b71242e (diff) | |
| download | coreboot-e8179b51380cf0922466c33a9a0998a65f246a84.tar.xz | |
Add ddr3lv_support flag to pei_data structure
This will enable DDR3 1.35V support for memory training in
the reference code. It requires the board to be setup for
1.35V with whatever board-specific GPIOs are available.
Change-Id: I14e4686c20f9610f90678e6e3bece8ba80d8621a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1825
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/pei_data.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 34adddc291..cabda3fea4 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -31,7 +31,7 @@ #define PEI_DATA_H typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 2 +#define PEI_VERSION 3 struct pei_data { uint32_t pei_version; @@ -98,6 +98,7 @@ struct pei_data */ uint8_t spd_data[4][256]; tx_byte_func tx_byte; + int ddr3lv_support; } __attribute__((packed)); #endif |