summaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-10-24 12:24:19 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2020-10-31 10:08:59 +0000
commitf5dd7b6eb9b247486406f387c1cdc8c893a8cdf4 (patch)
tree91bf20fbeb079c82c03d3e5395873abd461b17d4 /src/northbridge
parent8963f7d40be4961e8ae6dca4185e4e682ba2fdb9 (diff)
downloadcoreboot-f5dd7b6eb9b247486406f387c1cdc8c893a8cdf4.tar.xz
{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46720 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/haswell/finalize.c4
-rw-r--r--src/northbridge/intel/haswell/gma.c4
-rw-r--r--src/northbridge/intel/haswell/northbridge.c6
3 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c
index 1600a42625..b95b3fe3c9 100644
--- a/src/northbridge/intel/haswell/finalize.c
+++ b/src/northbridge/intel/haswell/finalize.c
@@ -22,10 +22,10 @@ void intel_northbridge_haswell_finalize_smm(void)
MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */
MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */
- MCHBAR32_OR(DMIVCLIM, 1UL << 31);
+ MCHBAR32_OR(DMIVCLIM, 1 << 31);
MCHBAR32_OR(CRDTLCK, 1 << 0);
MCHBAR32_OR(MCARBLCK, 1 << 0);
- MCHBAR32_OR(REQLIM, 1UL << 31);
+ MCHBAR32_OR(REQLIM, 1 << 31);
MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */
MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 66c8d2d40d..0bca230b64 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -196,7 +196,7 @@ static void gma_pm_init_pre_vbios(struct device *dev)
gtt_write_regs(haswell_gt_setup);
/* Wait for Mailbox Ready */
- gtt_poll(0x138124, (1UL << 31), (0UL << 31));
+ gtt_poll(0x138124, (1 << 31), (0 << 31));
/* Mailbox Data - RC6 VIDS */
gtt_write(0x138128, 0x00000000);
@@ -205,7 +205,7 @@ static void gma_pm_init_pre_vbios(struct device *dev)
gtt_write(0x138124, 0x80000004);
/* Wait for Mailbox Ready */
- gtt_poll(0x138124, (1UL << 31), (0UL << 31));
+ gtt_poll(0x138124, (1 << 31), (0 << 31));
/* Enable PM Interrupts */
gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT |
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 88ccd710f3..2d19ccdda5 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -31,18 +31,18 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *
switch ((pciexbar_reg >> 1) & 3) {
case 0: /* 256MB */
- mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
+ mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28);
*base = pciexbar_reg & mask;
*len = 256 * 1024 * 1024;
return 1;
case 1: /* 128M */
- mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
+ mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28);
mask |= (1 << 27);
*base = pciexbar_reg & mask;
*len = 128 * 1024 * 1024;
return 1;
case 2: /* 64M */
- mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
+ mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28);
mask |= (1 << 27) | (1 << 26);
*base = pciexbar_reg & mask;
*len = 64 * 1024 * 1024;