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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-22 20:11:49 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-24 09:36:06 +0000 |
| commit | 3dbfb2bef9cdb97ac6e34a4268cc4a26e6483013 (patch) | |
| tree | 3602e36a010ad3d4aed4efd4c9e4dd307ba1d64d /src/northbridge | |
| parent | 502008d5dc4467fc03e8a2edd7a50b340a4c5529 (diff) | |
| download | coreboot-3dbfb2bef9cdb97ac6e34a4268cc4a26e6483013.tar.xz | |
nb/amd/amdmct/mct/mctdqs_d.c: Remove variable set but not used
Change-Id: I45f32ea1ebf59a20d475dfad2d9d0980dec6918b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctdqs_d.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index e2dd56fc1a..36ee3ab332 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -1192,8 +1192,6 @@ void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr) { - u32 value; - /* BIOS issues the remaining (Ntrain - 2) reads after checking that * F2x11C[PrefDramTrainMode] is cleared. These reads must be to * consecutive cache lines (i.e., 64 bytes apart) and must not cross @@ -1205,5 +1203,5 @@ void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, SetUpperFSbase(addr); /* 1st move causes read fill (to exclusive or shared)*/ - value = read32_fs(addr << 8); + read32_fs(addr << 8); } |