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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-03 10:44:55 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-05 07:49:09 +0000 |
| commit | aa7cf5597b0f4d59c5d7fe42a8b5130852056bff (patch) | |
| tree | e7bcbf378dcca3971be89d8e916b1e111cc4a089 /src/northbridge | |
| parent | 2dcc3a5c68b4bacbe96c1543cc20e5a3425889fb (diff) | |
| download | coreboot-aa7cf5597b0f4d59c5d7fe42a8b5130852056bff.tar.xz | |
nb/intel/pineview: Switch to POSTCAR_STAGE
Change-Id: If23925e2837645c974e4094e7e2d90e700d3d9e8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/pineview/Kconfig | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/ram_calc.c | 14 |
3 files changed, 11 insertions, 7 deletions
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index e8ef9d9403..80f566acb6 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -29,6 +29,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select RELOCATABLE_RAMSTAGE select INTEL_GMA_ACPI + select POSTCAR_STAGE + select POSTCAR_CONSOLE config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index a4c08c8af1..d7936c1fbf 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -25,4 +25,6 @@ romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += early_init.c +postcar-y += ram_calc.c + endif diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index fd893bc87a..d116709cd9 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -107,9 +107,10 @@ void *cbmem_top(void) #define ROMSTAGE_RAM_STACK_SIZE 0x5000 -/* setup_stack_and_mtrrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -void *setup_stack_and_mtrrs(void) +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; @@ -132,8 +133,7 @@ void *setup_stack_and_mtrrs(void) postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); + + /* We do not return here. */ } |