AMD/CIMx: Add functions for AMD PCI IRQ routing

The PCI_INTR table is an Index/Data pair of I/O ports
0xC00 and 0xC01.  This table is responsible for physically
routing IRQs to the PIC and IOAPIC.  The settings given
in this table are chipset and mainboard dependent, so the
table values will reside in the mainboard.c file. This
allows for a system to uniquely set its IRQ routing.
The function to write the PCI_INTR table resides in
cimx_util.c because the indices into the table have
the same definitions for all SBx00 FCH chipsets.

The next piece is a function that will read the PCI_INTR
table and program the INT_LINE and INT_PIN registers in
PCI config space appropriately.  This function will read
a devices' INT_PIN register, which is always hardcoded to
a value if it uses hardware interrupts.  It then uses this
value, along with the device and function numbers to
determine an index into the PCI_INTR table.  It will read
the table and program the corresponding value into the PCI
config space register 0x3C, INT_LINE.  Finally, it will set
this IRQ number to LEVEL_TRIGGERED on the PIC because it is
a PCI device interrupt and the must be level triggered.

For example, the SB800 USB EHCI device 0:18.2 has an INT_PIN
value hardcoded to 2.  This corresponds to PIN B.  On the
Persimmon mainboard, I want the USB device to use IRQ 11.  I
will program the PCI_INTR table at index 0x31 (this USB device
index) to 11.  This function will then read the INT_PIN register,
read the PCI_INTR table, and then program the INT_LINE register
with the value it read.  It will then set the IRQ on the PIC to
LEVEL_TRIGGERED by writing a 1 to I/O port 0x4D1 at bit position 4.

Also, the SB700 has slightly different register definitions than
the newer SB800 and SB900 so it needs its own set of #defines for
the pci_intr registers.

Only the Persimmon mainboard is adapted to this change as an
example for other mainboards.

Change-Id: I6de858289a17fa1e1abacf6328ea5099be74b1d6
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5877
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

1 files changed, 54 insertions, 0 deletions

diff --git a/src/northbridge/amd/agesa/family14/pci_devs.h b/src/northbridge/amd/agesa/family14/pci_devs.h
new file mode 100644
index 0000000000..a9e95d1f94
--- /dev/null
+++ b/src/northbridge/amd/agesa/family14/pci_devs.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _AMD_FAM14_PCI_DEVS_H_
+#define _AMD_FAM14_PCI_DEVS_H_
+
+#define BUS0 0
+
+/* Graphics and Display */
+#define GFX_DEV 0x1
+#define GFX_FUNC 0
+# define GFX_DEVFN PCI_DEVFN(GFX_DEV,GFX_FUNC)
+
+/* PCI Ports */
+#define PCI_PORT_DEV 0x14
+#define PCI_PORT_FUNC 4
+# define PCI_PORT_DEVID 0x4384
+# define PCI_PORT_DEVFN PCI_DEVFN(PCI_PORT_DEV,PCI_PORT_FUNC)
+
+/* PCIe Ports */
+#define NB_PCIE_PORT1_DEV 0x4
+#define NB_PCIE_PORT2_DEV 0x5
+#define NB_PCIE_PORT3_DEV 0x6
+#define NB_PCIE_PORT4_DEV 0x7
+#define NB_PCIE_PORT5_DEV 0x8
+#define NB_PCIE_FUNC 0
+# define NB_PCIE_PORT1_DEVID 0x1512
+# define NB_PCIE_PORT2_DEVID 0x1513
+# define NB_PCIE_PORT3_DEVID 0x1514
+# define NB_PCIE_PORT4_DEVID 0x1515
+# define NB_PCIE_PORT5_DEVID 0x1516
+# define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_PCIE_PORT1_DEV,NB_PCIE_FUNC)
+# define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV,NB_PCIE_FUNC)
+# define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_PCIE_PORT3_DEV,NB_PCIE_FUNC)
+# define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_PCIE_PORT4_DEV,NB_PCIE_FUNC)
+# define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_PCIE_PORT5_DEV,NB_PCIE_FUNC)
+
+#endif /* _AMD_FAM14_PCI_DEVS_H_ */