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authorAngel Pons <th3fanbus@gmail.com>2020-06-11 13:28:03 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-06-12 09:37:47 +0000
commit22aeed307de770ac4d6cc0cb151a935a8840b10c (patch)
treee74ec4cc3f3c7f78e60e328669eaa6f3163b9eb2 /src/northbridge
parent304925714d6ba6f8e7ba68d33475fb1ae58f0390 (diff)
downloadcoreboot-22aeed307de770ac4d6cc0cb151a935a8840b10c.tar.xz
nb/intel/i945/rcven.c: Correct comment
The offset between registers has to be between different channels. Change-Id: Ic6d959c31c78073a3ecbf7a17dfb73ac36340599 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i945/rcven.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index ea37d9c4f3..0b5890410f 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -253,7 +253,7 @@ static int find_strobes_edge(int channel_offset, u8 *mediumcoarse, u8 *fine,
}
/**
- * Here we use a trick. The RCVEN channel 0 registers are all at an
+ * Here we use a trick. The RCVEN channel 1 registers are all at an
* offset of 0x80 to the channel 0 registers. We don't want to waste
* a lot of if ()s so let's just pass 0 or 0x80 for the channel offset.
*/