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authorDuncan Laurie <dlaurie@chromium.org>2012-12-19 09:12:31 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-03-14 20:16:26 +0100
commit26e7dd703dea8dce30829d8bb73c1f27a2178d72 (patch)
tree924161b457fd106535444b45089d3e0ede1dd8d9 /src/northbridge
parenteb58bc5af6b8bf626f38d0c07bf55db2835f53b5 (diff)
downloadcoreboot-26e7dd703dea8dce30829d8bb73c1f27a2178d72.tar.xz
haswell: more ULT/LP support and minor tweaks
- Add ME device ID for Lynxpoint LP - Add GPU device IDs for ULT - SATA init tweaks from checking against DXE reference code - Remove the ICH7 from the SPI driver so it works on all lynxpoint without having to add more LPC device ID checks - Add function disable for audio dsp and xhci, remove PCI bridge - Add interrupt route registers for new devices (needs romstage setup) Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2680 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/haswell/gma.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 79473d523a..d0850667ac 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -40,14 +40,17 @@ u32 map_oprom_vendev(u32 vendev)
case 0x80860402: /* GT1 Desktop */
case 0x80860406: /* GT1 Mobile */
case 0x8086040a: /* GT1 Server */
+ case 0x80860a06: /* GT1 ULT */
case 0x80860412: /* GT2 Desktop */
case 0x80860416: /* GT2 Mobile */
case 0x8086041a: /* GT2 Server */
+ case 0x80860a16: /* GT2 ULT */
case 0x80860422: /* GT3 Desktop */
case 0x80860426: /* GT3 Mobile */
case 0x8086042a: /* GT3 Server */
+ case 0x80860a26: /* GT3 ULT */
new_vendev=0x80860406; /* GT1 Mobile */
break;