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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-11-11 19:01:41 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-11-12 22:16:16 +0100
commit31ec0f325718fb0e5890ae0d662580415cd2e20e (patch)
tree62f3822f0a19b21f311b0a2dba1238eb4ec4ec5a /src/northbridge
parent7fd3ef57cba80f8ef2e9ecc500124e1e56d05325 (diff)
downloadcoreboot-31ec0f325718fb0e5890ae0d662580415cd2e20e.tar.xz
northbridge/amd/amdmct/mct_ddr3: Update prefetcher configuration
The existing prefetcher configuration was incorrect; use the correct values from the AMD Family 10h and Family 15h BKDGs as appropriate. Change-Id: I287ffa6345e1f4d232d4b2ea4251650ada3fda92 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12417 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index f696daeed9..b3f43fb422 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -2408,9 +2408,12 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat,
} while (!(val & (1 << Dr_MemClrStatus)));
}
- val = 0x0FE40FC0; /* BKDG recommended */
+ if (is_fam15h())
+ val = 0x0ce00f41; /* BKDG recommended */
+ else
+ val = 0x0fe40fc0; /* BKDG recommended */
val |= MCCH_FlushWrOnStpGnt; /* Set for S3 */
- Set_NB32(dev, 0x11C, val);
+ Set_NB32(dev, 0x11c, val);
}
static u8 NodePresent_D(u8 Node)