summaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
authorStefan Reinauer <stepan@coresystems.de>2009-02-27 23:09:55 +0000
committerStefan Reinauer <stepan@openbios.org>2009-02-27 23:09:55 +0000
commit3c7f46b42215502ecaee54c85f6d08dce9e21279 (patch)
tree2f526a49a0182348e5d9a24b0d4d57c1f2f97619 /src/northbridge
parent678d6140a5f75bde7b5a6b7ef296ebb7a3dda166 (diff)
downloadcoreboot-3c7f46b42215502ecaee54c85f6d08dce9e21279.tar.xz
Generic approach of putting BIOS tables at the end of memory
(in addition to their low locations) This adds the kontron 986LCD-M and the i945 as a sample. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i945/northbridge.c32
1 files changed, 23 insertions, 9 deletions
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 6aa9f2d545..9cb5cefe62 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -93,12 +93,18 @@ static uint32_t find_pci_tolm(struct bus *bus)
return tolm;
}
+#if HAVE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+uint64_t uma_memory_base=0, uma_memory_size=0;
+
static void pci_domain_set_resources(device_t dev)
{
uint32_t pci_tolm;
uint8_t tolud, reg8;
uint16_t reg16;
- unsigned long long tomk, tolmk;
+ unsigned long long tomk;
pci_tolm = find_pci_tolm(&dev->link[0]);
@@ -120,13 +126,13 @@ static void pci_domain_set_resources(device_t dev)
switch (reg8) {
case 0:
tseg_size = 1024;
- break;
+ break; /* TSEG = 1M */
case 1:
tseg_size = 2048;
- break;
+ break; /* TSEG = 2M */
case 2:
tseg_size = 8192;
- break;
+ break; /* TSEG = 8M */
}
printk_debug("%dM\n", tseg_size >> 10);
@@ -150,24 +156,32 @@ static void pci_domain_set_resources(device_t dev)
printk_debug("%dM UMA\n", uma_size >> 10);
tomk -= uma_size;
+
+ /* For reserving UMA memory in the memory map */
+ uma_memory_base = tomk * 1024ULL;
+ uma_memory_size = uma_size * 1024ULL;
}
/* The following needs to be 2 lines, otherwise the second
* number is always 0
*/
- printk_info("Available memory: %dK", tomk);
- printk_info(" (%dM)\n", (tomk >> 10));
-
- tolmk = tomk;
+ printk_info("Available memory: %dK", (uint32_t)tomk);
+ printk_info(" (%dM)\n", (uint32_t)(tomk >> 10));
/* Report the memory regions */
ram_resource(dev, 3, 0, 640);
- ram_resource(dev, 4, 768, (tolmk - 768));
+ ram_resource(dev, 4, 768, (tomk - 768));
if (tomk > 4 * 1024 * 1024) {
ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
}
assign_resources(&dev->link[0]);
+
+#if HAVE_HIGH_TABLES==1
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
}
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)