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authorKeith Hui <buurin@gmail.com>2020-05-05 23:00:48 -0400
committerPatrick Georgi <pgeorgi@google.com>2020-07-06 06:27:36 +0000
commit572d66abb695f8b0dc4f6bec0631ba961cd5b66b (patch)
tree613c506e591ff91c47a9629bec1b416c187d49c8 /src/northbridge
parent8ba85deb8f249a17ffa3e53b4c772ec783a3bdb8 (diff)
downloadcoreboot-572d66abb695f8b0dc4f6bec0631ba961cd5b66b.tar.xz
nb/intel/i440bx: Add PMCR register to ACPI code
p3b-f suspend code is going to use it. Change-Id: Iebc17257e9f690115ec35d94c7c36df39341f0df Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41092 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
index ce71aedaee..98d06fb8e1 100644
--- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
+++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
@@ -9,6 +9,8 @@ Device (NB)
{
Offset (0x67), // DRB7
DRB7, 8,
+ Offset (0x7A), // PMCR
+ PMCR, 8
}
Method(TOM1, 0) {
/* Multiply by 8MB to get TOM */