diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 16:56:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:31:11 +0000 |
| commit | 67573371d5ade1ad388316585901ee9d0edfe512 (patch) | |
| tree | c925a49f9a2dcda5ad0ab1b828054ecf409ec00f /src/northbridge | |
| parent | 45008930626bda902c8f37880e6f09d517b8cdd2 (diff) | |
| download | coreboot-67573371d5ade1ad388316585901ee9d0edfe512.tar.xz | |
nb/intel/ironlake: Add SAD DRAM register definitions
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I66b87d15f6b741c6fc935106c35b201fbd9ab2c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/ironlake/ironlake.h | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/ironlake/raminit.c | 8 |
2 files changed, 7 insertions, 4 deletions
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index afd30823d5..fa59565ba8 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -57,6 +57,9 @@ #define SAD_PCIEXBAR 0x50 +#define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */ +#define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */ + /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index ecfbd8a3d1..f8f6b74466 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1337,9 +1337,9 @@ static void program_board_delay(struct raminfo *info) MCHBAR16_OR(0x612, 0x100); MCHBAR16_OR(0x214, 0x3E00); for (i = 0; i < 8; i++) { - pci_write_config32(QPI_SAD, 0x80 + 4 * i, + pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i), (info->total_memory_mb - 64) | !i | 2); - pci_write_config32(QPI_SAD, 0xc0 + 4 * i, 0); + pci_write_config32(QPI_SAD, SAD_INTERLEAVE_LIST(i), 0); } } @@ -1452,10 +1452,10 @@ static void program_total_memory_map(struct raminfo *info) memory_map[1] = 4096; for (i = 0; i < ARRAY_SIZE(memory_map); i++) { current_limit = MAX(current_limit, memory_map[i] & ~1); - pci_write_config32(QPI_SAD, 4 * i + 0x80, + pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i), (memory_map[i] & 1) | ALIGN_DOWN(current_limit - 1, 64) | 2); - pci_write_config32(QPI_SAD, 4 * i + 0xc0, 0); + pci_write_config32(QPI_SAD, SAD_INTERLEAVE_LIST(i), 0); } } |