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authorAngel Pons <th3fanbus@gmail.com>2020-06-22 18:23:17 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-07-01 18:15:15 +0000
commit68ab745086c6a062b5cb915424520bd0b18f7849 (patch)
tree2d925bb5401cb455cf703a5e9adb7882cba1f5f9 /src/northbridge
parentdd6a3d841b3903a69cacc79890e04ebfe3de5de3 (diff)
downloadcoreboot-68ab745086c6a062b5cb915424520bd0b18f7849.tar.xz
nb/intel/ironlake: Simplify BAR handling
Currently, northbridge BARs are 32-bit values. We don't have any use case for BARs above 4 GiB in early stages, so handling possibly 64-bit values seems unnecessary, which currently is a noisy way to write zero. Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I93d1740b961f6a5962757d9a1e960b3f1014a0c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/ironlake/early_init.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c
index b6c5f0fe34..acc76dabc6 100644
--- a/src/northbridge/intel/ironlake/early_init.c
+++ b/src/northbridge/intel/ironlake/early_init.c
@@ -38,15 +38,11 @@ static void ironlake_setup_bars(void)
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4,
- (0LL + DEFAULT_EPBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4,
- (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32);
-
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0);
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4,
- (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30);