diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 13:05:10 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-09 16:23:16 +0000 |
| commit | 6e1c471f701b8ba1e9c07a87ecc73c8d855478dd (patch) | |
| tree | d0dad464e0d99f807bb7e0f183f76170fbd3f02c /src/northbridge | |
| parent | 2cb3cc52380818c8301a7cd6f9a1295147d01186 (diff) | |
| download | coreboot-6e1c471f701b8ba1e9c07a87ecc73c8d855478dd.tar.xz | |
haswell: Turn RCBA configuration into a function
Instead of passing around a pointer to an array, just write the relevant
registers directly. Note that intel/baskingridge used spaces to indent
line continuations and had to be replaced with tabs to quell Jenkins.
Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 2 |
2 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index b98d88085e..1ec4cd1cb9 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -190,11 +190,9 @@ void intel_northbridge_haswell_finalize_smm(void); struct pei_data; -struct rcba_config_instruction; struct romstage_params { struct pei_data *pei_data; const void *gpio_map; - const struct rcba_config_instruction *rcba_config; void (*copy_spd)(struct pei_data *peid); }; void romstage_common(const struct romstage_params *params); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 579eca791b..c3d9a1088a 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -19,7 +19,7 @@ void romstage_common(const struct romstage_params *params) enable_lapic(); - wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); + wake_from_s3 = early_pch_init(params->gpio_map); /* Perform some early chipset initialization required * before RAM initialization can work |