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| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-07 19:30:26 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-09 00:33:53 +0000 |
| commit | 71892b4bec8db6ef590e40265586c636788b105d (patch) | |
| tree | ff8d31c35a092d38f46a7f7dd95a9a72bb36e98c /src/northbridge | |
| parent | 9733f6a33687547a9a38589468a2b7b2b927461f (diff) | |
| download | coreboot-71892b4bec8db6ef590e40265586c636788b105d.tar.xz | |
nb/intel/sandybridge: Use MCHBAR bitwise ops
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: If16d8c4aef3dfd1dbeaf48d6855dd4c0ef328168
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 20 |
1 files changed, 5 insertions, 15 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 0c9325da41..2ee273c1f4 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -62,7 +62,6 @@ static void sandybridge_setup_bars(void) static void sandybridge_setup_graphics(void) { - u32 reg32; u16 reg16; u8 gfxsize; @@ -106,27 +105,18 @@ static void sandybridge_setup_graphics(void) pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); /* Erratum workarounds */ - reg32 = MCHBAR32(SAPMCTL); - reg32 |= (1 << 9) | (1 << 10); - MCHBAR32(SAPMCTL) = reg32; + MCHBAR32_OR(SAPMCTL, (1 << 9) | (1 << 10)); /* Enable SA Clock Gating */ - reg32 = MCHBAR32(SAPMCTL); - MCHBAR32(SAPMCTL) = reg32 | 1; + MCHBAR32_OR(SAPMCTL, 1); /* GPU RC6 workaround for sighting 366252 */ - reg32 = MCHBAR32(SSKPD_HI); - reg32 |= (1 << 31); - MCHBAR32(SSKPD_HI) = reg32; + MCHBAR32_OR(SSKPD_HI, 1 << 31); /* VLW (Virtual Legacy Wire?) */ - reg32 = MCHBAR32(0x6120); - reg32 &= ~(1 << 0); - MCHBAR32(0x6120) = reg32; + MCHBAR32_AND(0x6120, ~(1 << 0)); - reg32 = MCHBAR32(INTRDIRCTL); - reg32 |= (1 << 4) | (1 << 5); - MCHBAR32(INTRDIRCTL) = reg32; + MCHBAR32_OR(INTRDIRCTL, (1 << 4) | (1 << 5)); } static void start_peg_link_training(void) |