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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2007-05-28 14:37:06 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2007-05-28 14:37:06 +0000 |
| commit | 861f96403777c8f4475ca94613c5142075dd0cdf (patch) | |
| tree | 42d15ba06ada33c66f4654dd27f7d84e70a7aeca /src/northbridge | |
| parent | f5a6fd253c3d289bd70917504f59255038d476a2 (diff) | |
| download | coreboot-861f96403777c8f4475ca94613c5142075dd0cdf.tar.xz | |
Lower the RAM init delays we use on the Intel 440BX.
As per JEDEC, we should wait 200us until voltages and clocks are stable.
Then apply NOPs for 200 clock cycles (for simplicity we use 200us here).
All other delays are so low that we get away with just waiting 1us.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/i440bx/raminit.c | 21 |
1 files changed, 9 insertions, 12 deletions
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index b51a0e67b4..19990b5b70 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -509,44 +509,41 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) { int i; - /* TODO: Use a delay here? Needed? */ - mdelay(200); + /* 0. Wait until power/voltages and clocks are stable (200us). */ + udelay(200); - /* TODO: How long should the delays be? Fix later. */ - - /* 1. Apply NOP. */ + /* 1. Apply NOP. Wait 200 clock cycles (200us should do). */ PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); do_ram_command(ctrl, RAM_COMMAND_NOP, 0); - mdelay(10); + udelay(200); /* 2. Precharge all. Wait tRP. */ PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0); - mdelay(10); + udelay(1); /* 3. Perform 8 refresh cycles. Wait tRC each time. */ PRINT_DEBUG("RAM Enable 3: CBR\r\n"); for (i = 0; i < 8; i++) { do_ram_command(ctrl, RAM_COMMAND_CBR, 0); - mdelay(10); + udelay(1); } /* 4. Mode register set. Wait two memory cycles. */ PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0); - mdelay(10); - mdelay(10); + udelay(2); /* 5. Normal operation. */ PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0); - mdelay(10); + udelay(1); /* 6. Finally enable refresh. */ PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n"); // pci_write_config8(ctrl->d0, PMCR, 0x10); spd_enable_refresh(ctrl); - mdelay(10); + udelay(1); PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); DUMPNORTH(); |