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authorAaron Durbin <adurbin@chromium.org>2013-02-15 21:45:06 -0600
committerRonald G. Minnich <rminnich@gmail.com>2013-03-21 22:59:03 +0100
commit8ce667e50684bea7c60db43c0ca7dd1b3ec3fde3 (patch)
tree5f68514d230ee7ebd0c60c9c667403ab06adf17b /src/northbridge
parent67481ddc2e53cd3420fa8c723edb4fe47dccc196 (diff)
downloadcoreboot-8ce667e50684bea7c60db43c0ca7dd1b3ec3fde3.tar.xz
haswell: add multipurpose SMM memory region
The SMM region is available for multipurpose use before the SMM handler is relocated. Provide a configurable sized region in the TSEG for use before the SMM handler is relocated. This feature is implemented by making the reserved size a Kconfig option. Also make the IED region a Kconfig option as well. Lastly add some sanity checking on the Kconfig options. Change-Id: Idd7fccf925a8787146906ac766b7878845c75935 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2804 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/haswell/haswell.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 3a1803858a..ba88722452 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -43,8 +43,8 @@
#define IVB_STEP_K0 (BASE_REV_IVB + 5)
#define IVB_STEP_D0 (BASE_REV_IVB + 6)
-/* Intel Enhanced Debug region must be 4MB */
-#define IED_SIZE 0x400000
+/* Intel Enhanced Debug region */
+#define IED_SIZE CONFIG_IED_REGION_SIZE
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */