summaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-06-27 17:52:45 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-11-15 02:45:37 +0100
commita44daac7e6b7b4794f8346c9ae1e998e4f692e83 (patch)
tree6336ff1014e7660e69cf0dd306d347a4b2a8b5b8 /src/northbridge
parent4ef4fc6c3bc9bb65d9336c9b695ed53a05fe0151 (diff)
downloadcoreboot-a44daac7e6b7b4794f8346c9ae1e998e4f692e83.tar.xz
northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot failure
In the course of adding full Family 15h MCT support some Family 15h specific settings were inadvertently applied to Family 10h processors. Only apply Family15h specific settings to Family 15h processors. Change-Id: I5dcb333d3a5a49318fe7bddd4c386642205c343e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12013 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c28
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c8
2 files changed, 28 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index e7fee19b3f..c8d72c6702 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -1635,6 +1635,11 @@ restartinit:
HTMemMapInit_D(pMCTstat, pDCTstatA); /* Map local memory into system address space.*/
mctHookAfterHTMap();
+ if (!is_fam15h()) {
+ printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n");
+ CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */
+ }
+
printk(BIOS_DEBUG, "mctAutoInitMCT_D: mctHookAfterCPU\n");
mctHookAfterCPU(); /* Setup external northbridge(s) */
@@ -1658,6 +1663,11 @@ restartinit:
printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n");
DQSTiming_D(pMCTstat, pDCTstatA, allow_config_restore); /* Get Receiver Enable and DQS signal timing*/
+ if (!is_fam15h()) {
+ printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n");
+ UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */
+ }
+
if (!allow_config_restore) {
printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n");
mct_OtherTiming(pMCTstat, pDCTstatA);
@@ -1678,11 +1688,13 @@ restartinit:
MCTMemClr_D(pMCTstat,pDCTstatA);
}
- printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n");
- CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */
+ if (is_fam15h()) {
+ printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n");
+ CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */
- printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n");
- UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */
+ printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n");
+ UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */
+ }
printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n");
for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
@@ -6353,11 +6365,13 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat,
DramMRS |= 1 << 1;
dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x84);
- dword |= DramMRS;
- if (is_fam15h())
+ if (is_fam15h()) {
+ dword |= DramMRS;
dword &= ~0x00800003;
- else
+ } else {
dword &= ~0x00fc2f8f;
+ dword |= DramMRS;
+ }
Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x84, dword);
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index 4397ebaccb..38991c813f 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -904,9 +904,15 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
* Flush the receiver FIFO
* Write one full cache line of non-0x55/0xaa data to one of the test addresses, then read it back to flush the FIFO
*/
-
+ /* FIXME
+ * This does not seem to be needed, and has a tendency to lock up the
+ * boot process while attempting to write the test pattern.
+ */
+#if 0
+ SetUpperFSbase(TestAddr0);
WriteLNTestPattern(TestAddr0 << 8, (uint8_t *)TestPattern2_D, 1);
mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0);
+#endif
}
MaxDelay_CH[Channel] = CTLRMaxDelay;
}