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| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2009-06-05 23:43:11 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2009-06-05 23:43:11 +0000 |
| commit | aa58f5427ff5188bc867b1016ca2a41e0a516519 (patch) | |
| tree | b19e9bc3c2016e8ee4c8e86c18729ecb58dfa761 /src/northbridge | |
| parent | 20a98c9201a0a3699e64c2c2dc4c6259ae948ade (diff) | |
| download | coreboot-aa58f5427ff5188bc867b1016ca2a41e0a516519.tar.xz | |
Fix non-revF K8 ram init compilation which was broken in r4341.
Change all printk_raminit to printk_spew.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 690a4a0a7c..e55f4b898f 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -855,12 +855,12 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) /* Now set top of memory */ msr_t msr; if (tom_k > (4*1024*1024)) { - printk_raminit("Handling memory mapped above 4 GB\n"); - printk_raminit("Upper RAM end at 0x%08x kB\n", tom_k); + printk_spew("Handling memory mapped above 4 GB\n"); + printk_spew("Upper RAM end at 0x%08x kB\n", tom_k); msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM2, msr); - printk_raminit("Correcting memory amount mapped below 4 GB\n"); + printk_spew("Correcting memory amount mapped below 4 GB\n"); } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 @@ -873,9 +873,9 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) } else #endif tom_k = 0x3f0000; - printk_raminit("Adjusting lower RAM end\n"); + printk_spew("Adjusting lower RAM end\n"); } - printk_raminit("Lower RAM end at 0x%08x kB\n", tom_k); + printk_spew("Lower RAM end at 0x%08x kB\n", tom_k); msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(TOP_MEM, msr); @@ -2106,7 +2106,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) return; hw_spd_err: /* Unrecoverable error reading SPD data */ - print_err("SPD error - reset\n"); + printk_err("SPD error - reset\n"); hard_reset(); return; } @@ -2172,7 +2172,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; - printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk); + printk_spew("Handling memory hole at 0x%08x (default)\n", hole_startk); #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 /* We need to double check if hole_startk is valid. * If it is equal to the dram base address in K (base_k), @@ -2197,7 +2197,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) basek_pri = base_k; } - printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk); + printk_spew("Handling memory hole at 0x%08x (adjusted)\n", hole_startk); #endif /* Find node number that needs the memory hole configured */ for (i=0; i<controllers; i++) { |