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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-11-24 14:12:02 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-01 22:56:33 +0100 |
| commit | b410d267e33ca2e4a154fc2cb0221d1afed18a56 (patch) | |
| tree | 02bd28bb24ebbc1bf62e839c03c76d39d4cc49a1 /src/northbridge | |
| parent | e79cb5e19dbb7927e5319e258d06c2c34dd2ad0d (diff) | |
| download | coreboot-b410d267e33ca2e4a154fc2cb0221d1afed18a56.tar.xz | |
nb/amd/amdmct/mct_ddr3: Save and restore SkewMemClk for S3 resume
Change-Id: Ib331bd330530d4d6be5eb7351d9f9b15c135dd63
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13167
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 5 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 6 |
2 files changed, 9 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index e7361ac587..f953919052 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -729,7 +729,7 @@ struct amd_s3_persistent_mct_channel_data { uint32_t f3x5c; uint32_t f3x60; - /* Family 15h-specific registers (90 dwords) */ + /* Family 15h-specific registers (91 dwords) */ uint32_t f2x200; uint32_t f2x204; uint32_t f2x208; @@ -785,8 +785,9 @@ struct amd_s3_persistent_mct_channel_data { uint32_t f2x9cx0d0fc231; uint32_t f2x9cx0d0f0_0_f_31[9]; /* [lane] */ uint32_t f2x9cx0d0f8021; + uint32_t f2x9cx0d0fe00a; - /* TOTAL: 342 dwords */ + /* TOTAL: 343 dwords */ } __attribute__((packed)); struct amd_s3_persistent_node_data { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index ae2cca1e91..fe7707591e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -454,6 +454,9 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da data->f2x9cx0d0f0_0_f_31[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0031 | (i << 8)); data->f2x9cx0d0f8021 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8021); + + if (channel == 1) + data->f2x9cx0d0fe00a = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe00a); } /* Stage 4 */ @@ -796,6 +799,9 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0031 | (i << 8), data->f2x9cx0d0f0_0_f_31[i]); write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8021, data->f2x9cx0d0f8021); + + if (channel == 1) + write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe00a, data->f2x9cx0d0fe00a); } } } |