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authorAaron Durbin <adurbin@chromium.org>2012-11-12 10:14:55 -0600
committerRonald G. Minnich <rminnich@gmail.com>2013-03-14 05:07:21 +0100
commitb9adf7ba4bf6e8f11bf174973230c5317cbb3b6d (patch)
tree6dedc4658f2ec9ca30edd70277f86e57aef1112d /src/northbridge
parentf6933a6f56f8bdc7e249b6629824acce646d5f6a (diff)
downloadcoreboot-b9adf7ba4bf6e8f11bf174973230c5317cbb3b6d.tar.xz
haswell: use #defines for constants in udelay.c
Change the hard coded values in udelay.c to use the #defines for MSRs and BCLK. Change-Id: I2bbeb0b478d2e3ca155e8f82006df86c29a4f018 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2629 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/haswell/udelay.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/src/northbridge/intel/haswell/udelay.c b/src/northbridge/intel/haswell/udelay.c
index 864e83915c..f5d541e8e1 100644
--- a/src/northbridge/intel/haswell/udelay.c
+++ b/src/northbridge/intel/haswell/udelay.c
@@ -21,10 +21,7 @@
#include <stdint.h>
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
-
-/**
- * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz
- */
+#include "cpu/intel/haswell/haswell.h"
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
@@ -42,13 +39,13 @@ void udelay(u32 us)
u32 dword;
tsc_t tsc, tsc1, tscd;
msr_t msr;
- u32 fsb = 100, divisor;
+ u32 divisor;
u32 d; /* ticks per us */
- msr = rdmsr(0xce);
+ msr = rdmsr(MSR_PLATFORM_INFO);
divisor = (msr.lo >> 8) & 0xff;
- d = fsb * divisor; /* On Core/Core2 this is divided by 4 */
+ d = HASWELL_BCLK * divisor;
multiply_to_tsc(&tscd, us, d);
tsc1 = rdtsc();