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authorDuncan Laurie <dlaurie@chromium.org>2013-01-10 13:23:48 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-03-14 05:03:51 +0100
commitce36b12c2702d88e95e5c0294035bcd5e1de22ab (patch)
treef15b48df91b7b5e316e28a1031770426e15a1e6a /src/northbridge
parent67113e95cf054e051c63e813814b91f909798ac9 (diff)
downloadcoreboot-ce36b12c2702d88e95e5c0294035bcd5e1de22ab.tar.xz
haswell: Add LPT LP device IDs to platform report
Boot haswell ULT and see LPT reported properly. Change-Id: I48344a8dde6adbbf331c91231342de45b1b6c32a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2697 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/haswell/report_platform.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index c65bbe5faa..6db8ae09a3 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -86,6 +86,10 @@ static struct {
{0x8c54, "C224"},
{0x8c56, "C226"},
{0x8c5c, "H81"},
+ {0x9c41, "LP Full Featured Engineering Sample"},
+ {0x9c43, "LP Premium"},
+ {0x9c45, "LP Mainstream"},
+ {0x9c47, "LP Value"},
};
static void report_pch_info(void)