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authorElyes HAOUAS <ehaouas@noos.fr>2016-09-17 20:48:29 +0200
committerPatrick Georgi <pgeorgi@google.com>2016-09-20 17:38:01 +0200
commitd4fea5c67587114f2be4c3235f4eb9c8d70df6ed (patch)
tree988f7983b3a1c81fefe6054f4a00a3631fa6ba61 /src/northbridge
parenta3d15afc675b8030c692af6ff918d6b67255c2d7 (diff)
downloadcoreboot-d4fea5c67587114f2be4c3235f4eb9c8d70df6ed.tar.xz
northbridge/intel/fsp_rangeley: Add space around operators
Change-Id: Ia60729db83333c1159862cf604de321e3af8dcb1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16631 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c2
-rw-r--r--src/northbridge/intel/fsp_rangeley/northbridge.c1
-rw-r--r--src/northbridge/intel/fsp_rangeley/udelay.c2
3 files changed, 2 insertions, 3 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
index 2ac1a2363a..6a33eda202 100644
--- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
@@ -170,7 +170,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
void ChipsetFspReturnPoint(EFI_STATUS Status,
VOID *HobListPtr)
{
- *(void **)CBMEM_FSP_HOB_PTR=HobListPtr;
+ *(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
if (Status == 0xFFFFFFFF) {
soft_reset();
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c
index b2ae3c4a08..f01333e4a0 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.c
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.c
@@ -86,7 +86,6 @@ static int add_fixed_resources(struct device *dev, int index)
struct resource *resource;
u32 pcie_config_base, pcie_config_size;
-
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
"size=0x%x\n", pcie_config_base, pcie_config_size);
diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c
index e599e00482..5aca22974f 100644
--- a/src/northbridge/intel/fsp_rangeley/udelay.c
+++ b/src/northbridge/intel/fsp_rangeley/udelay.c
@@ -19,7 +19,7 @@
#include <cpu/x86/msr.h>
/**
- * Intel Rangeley CPUs always run the TSC at BCLK=100MHz
+ * Intel Rangeley CPUs always run the TSC at BCLK = 100MHz
*/
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow.